公开(公告)号：US09741720B1

公开(公告)日：2017-08-22

申请号：US15219967

申请日：2016-07-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shahab Siddiqui ,  Balaji Kannan ,  Siddarth Krishnan

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/51 ,  H01L21/02

CPC classification number: H01L27/0924 ,  H01L21/0228 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor structure includes a semiconductor substrate, n-type and p-type FinFETs on the substrate, each of the n-type and the p-type FinFETs include a channel region and a gate structure surrounding the channel region, each gate structure having a phase-changed high-k gate dielectric layer lining a gate trench thereof, the gate trench defined by a pair of spacers. The semiconductor structure further includes a conformal dielectric capping layer over each phase-changed high-k gate dielectric layer, the conformal dielectric capping layer having a higher dielectric constant than the phase-changed high-k gate dielectric layer. Further included on the n-type FinFETs is a multi-layer replacement gate stack of n-type work function material over the phase-changed high-k gate dielectric layer. A method of fabricating the semiconductor structure is also provided.

公开(公告)号：US09748145B1

公开(公告)日：2017-08-29

申请号：US15055826

申请日：2016-02-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Balaji Kannan ,  Unoh Kwon ,  Siddarth Krishnan ,  Takashi Ando ,  Vijay Narayanan

IPC: H01L21/8238 ,  H01L21/324 ,  H01L21/225 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L29/66545 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518

Abstract: Semiconductor device fabrication methods are provided which include: providing a structure with at least one region and including a dielectric layer disposed over a substrate; forming a multilayer stack structure including a threshold-voltage adjusting layer over the dielectric layer, the multilayer stack structure including a first threshold-voltage adjusting layer in a first region of the at least one region, and a second threshold-voltage adjusting layer in a second region of the at least one region; and annealing the structure to define a varying threshold voltage of the at least one region, the annealing facilitating diffusion of at least one threshold voltage adjusting species from the first threshold-voltage adjusting layer and the second threshold-voltage adjusting layer into the dielectric layer, where a threshold voltage of the first region is independent of the threshold voltage of the second region.