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1.发明授权公开(公告)号：US09806161B1
公开(公告)日：2017-10-31
申请号：US15092910
申请日：2016-04-07
申请人： GLOBALFOUNDRIES INC.
IPC分类号： H01L29/423 , H01L21/311 , H01L29/51 , H01L21/033 , H01L21/84 , H01L21/027 , H01L21/8234 , H01L27/12
CPC分类号： H01L29/42364 , H01L21/0273 , H01L21/0332 , H01L21/28202 , H01L21/31133 , H01L21/31144 , H01L21/823431 , H01L21/823462 , H01L21/845 , H01L27/1207 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/66545
摘要： One aspect of the disclosure relates to and integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a thin gate dielectric device on a substrate, the thin gate dielectric device including: a first interfacial layer over a set of fins within the substrate, wherein the interfacial layer has a thickness of approximately 1.0 nanometers (nm) to approximately 1.2 nm; and a thick gate dielectric device on the substrate adjacent to the thin gate dielectric device, the thick gate dielectric device including: a second interfacial layer over the set of fins within the substrate; and a nitrided oxide layer over the second interfacial layer, wherein the nitrided oxide layer includes a thickness of approximately 3.5 nm to approximately 5.0 nm.
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2.发明申请公开(公告)号：US20170294519A1
公开(公告)日：2017-10-12
申请号：US15092910
申请日：2016-04-07
申请人： GLOBALFOUNDRIES INC.
IPC分类号： H01L29/423 , H01L21/027 , H01L29/51 , H01L21/8234 , H01L21/033 , H01L27/12 , H01L21/84 , H01L21/311
CPC分类号： H01L29/42364 , H01L21/0273 , H01L21/0332 , H01L21/28202 , H01L21/31133 , H01L21/31144 , H01L21/823431 , H01L21/823462 , H01L21/845 , H01L27/1207 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/66545
摘要： One aspect of the disclosure relates to and integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a thin gate dielectric device on a substrate, the thin gate dielectric device including: a first interfacial layer over a set of fins within the substrate, wherein the interfacial layer has a thickness of approximately 1.0 nanometers (nm) to approximately 1.2 nm; and a thick gate dielectric device on the substrate adjacent to the thin gate dielectric device, the thick gate dielectric device including: a second interfacial layer over the set of fins within the substrate; and a nitrided oxide layer over the second interfacial layer, wherein the nitrided oxide layer includes a thickness of approximately 3.5 nm to approximately 5.0 nm.
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公开(公告)号：US10361289B1
公开(公告)日：2019-07-23
申请号：US15933032
申请日：2018-03-22
申请人： GLOBALFOUNDRIES Inc.
发明人： Wei Zhao , Shahab Siddiqui , Haiting Wang , Ting-Hsiang Hung , Yiheng Xu , Beth Baumert , Jinping Liu , Scott Beasor , Yue Zhong , Shesh Mani Pandey
摘要： A method of thermally oxidizing a Si fin to form an oxide layer over the Si fin and then forming an ALD oxide layer over the oxide layer and resulting device are provided. Embodiments include forming a plurality of Si fins on a Si substrate; forming a dielectric layer over the plurality of Si fins and the Si substrate; recessing the dielectric layer, exposing a top portion of the plurality of Si fins; thermally oxidizing surface of the top portion of the plurality of Si fins, an oxide layer formed; and forming an ALD oxide layer over the oxide layer.
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公开(公告)号：US10106892B1
公开(公告)日：2018-10-23
申请号：US15692816
申请日：2017-08-31
申请人： GLOBALFOUNDRIES Inc.
IPC分类号： H01L21/02 , H01L21/306 , C23C16/455 , C01B33/149 , C01B21/06 , C01F7/02 , C01F17/00
摘要： Methods of forming conformal low temperature gate oxides on a HV I/O and a core logic and the resulting devices are provided. Embodiments include providing a HV I/O and core logic laterally separated on a Si substrate, each having a fin; forming a gate oxide layer over each fin and the Si substrate; forming a silicon oxy-nitride layer over the gate oxide layer; forming a sacrificial oxide layer over the silicon oxy-nitride layer; removing the sacrificial oxide and silicon oxy-nitride layers and thinning the gate oxide layer; forming a second gate oxide layer over the thinned gate oxide layer; forming a silicon oxy-nitride layer over the second gate oxide layer; removing the silicon oxy-nitride and second gate oxide layers over the core logic fin portion; forming an IL over the core logic fin portion; and forming a HfOx layer over the second silicon oxy-nitride layer and ILs.
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公开(公告)号：US10438853B2
公开(公告)日：2019-10-08
申请号：US15821684
申请日：2017-11-22
申请人： GLOBALFOUNDRIES INC.
IPC分类号： H01L21/8234 , C23C16/455 , H01L21/02 , H01L21/28 , H01L27/088 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/66 , H01L21/311 , C23C16/50
摘要： At least one method, apparatus and system are provided for forming a hybrid oxide layer for providing for a first region of a finFET device to operate at a first voltage and a second region of the finFET to operate at a second voltage. A first set of fins are formed on an I/O device portion, and a second set of fins are formed on a core device portion of a substrate. A first and a second oxide layers are deposited on the first and second set of fins, wherein they merge to form a hybrid oxide layer. The thickness of the second oxide layer is based on a first operating voltage for the I/O device portion. The hybrid layer is removed from the core device portion such that the I/O device portion operates at the first voltage and the core device portion operates at a second voltage.
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公开(公告)号：US09741720B1
公开(公告)日：2017-08-22
申请号：US15219967
申请日：2016-07-26
申请人： GLOBALFOUNDRIES Inc.
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/66 , H01L29/51 , H01L21/02
CPC分类号： H01L27/0924 , H01L21/0228 , H01L21/823821 , H01L21/823842 , H01L21/823857 , H01L29/517 , H01L29/66545
摘要： A semiconductor structure includes a semiconductor substrate, n-type and p-type FinFETs on the substrate, each of the n-type and the p-type FinFETs include a channel region and a gate structure surrounding the channel region, each gate structure having a phase-changed high-k gate dielectric layer lining a gate trench thereof, the gate trench defined by a pair of spacers. The semiconductor structure further includes a conformal dielectric capping layer over each phase-changed high-k gate dielectric layer, the conformal dielectric capping layer having a higher dielectric constant than the phase-changed high-k gate dielectric layer. Further included on the n-type FinFETs is a multi-layer replacement gate stack of n-type work function material over the phase-changed high-k gate dielectric layer. A method of fabricating the semiconductor structure is also provided.
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公开(公告)号：US09252232B2
公开(公告)日：2016-02-02
申请号：US14640735
申请日：2015-03-06
申请人： GLOBALFOUNDRIES INC.
IPC分类号： H01L21/02 , H01L27/088 , H01L29/51 , H01L27/12 , H01L21/28 , H01L21/324 , H01L29/06 , H01L29/10 , H01L29/16 , H01L29/161 , H01L29/423 , H01L21/8234
CPC分类号： H01L29/513 , H01L21/0214 , H01L21/02164 , H01L21/022 , H01L21/02236 , H01L21/02238 , H01L21/02247 , H01L21/02249 , H01L21/02252 , H01L21/02255 , H01L21/0228 , H01L21/02318 , H01L21/02326 , H01L21/02329 , H01L21/0234 , H01L21/2807 , H01L21/28185 , H01L21/28202 , H01L21/324 , H01L21/823412 , H01L27/088 , H01L27/1203 , H01L29/0649 , H01L29/1033 , H01L29/16 , H01L29/161 , H01L29/42364 , H01L29/518
摘要： A gate dielectric can be formed by depositing a first silicon oxide material by a first atomic layer deposition process. The thickness of the first silicon oxide material is selected to correspond to at least 10 deposition cycles of the first atomic layer deposition process. The first silicon oxide material is converted into a first silicon oxynitride material by a first plasma nitridation process. A second silicon oxide material is subsequently deposited by a second atomic layer deposition process. The second silicon oxide material is converted into a second silicon oxynitride material by a second plasma nitridation process. Multiple repetitions of the atomic layer deposition process and the plasma nitridation process provides a silicon oxynitride material having a ratio of nitrogen atoms to oxygen atoms greater than 1/3, which can be advantageously employed to reduce the leakage current through a gate dielectric.
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公开(公告)号：US20190157157A1
公开(公告)日：2019-05-23
申请号：US15821684
申请日：2017-11-22
申请人： GLOBALFOUNDRIES INC.
IPC分类号： H01L21/8234 , H01L21/02 , H01L21/28 , H01L27/088 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/66 , H01L21/311 , C23C16/50 , C23C16/455
摘要： At least one method, apparatus and system are provided for forming a hybrid oxide layer for providing for a first region of a finFET device to operate at a first voltage and a second region of the finFET to operate at a second voltage. A first set of fins are formed on an I/O device portion, and a second set of fins are formed on a core device portion of a substrate. A first and a second oxide layers are deposited on the first and second set of fins, wherein they merge to form a hybrid oxide layer. The thickness of the second oxide layer is based on a first operating voltage for the I/O device portion. The hybrid layer is removed from the core device portion such that the I/O device portion operates at the first voltage and the core device portion operates at a second voltage.
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公开(公告)号：US09196700B2
公开(公告)日：2015-11-24
申请号：US14640698
申请日：2015-03-06
申请人： GLOBALFOUNDRIES INC.
IPC分类号： H01L21/02 , H01L29/51 , H01L27/088 , H01L27/12 , H01L21/28 , H01L21/324 , H01L29/06 , H01L29/10 , H01L29/16 , H01L29/161 , H01L29/423 , H01L21/8234
CPC分类号： H01L29/513 , H01L21/0214 , H01L21/02164 , H01L21/022 , H01L21/02236 , H01L21/02238 , H01L21/02247 , H01L21/02249 , H01L21/02252 , H01L21/02255 , H01L21/0228 , H01L21/02318 , H01L21/02326 , H01L21/02329 , H01L21/0234 , H01L21/2807 , H01L21/28185 , H01L21/28202 , H01L21/324 , H01L21/823412 , H01L27/088 , H01L27/1203 , H01L29/0649 , H01L29/1033 , H01L29/16 , H01L29/161 , H01L29/42364 , H01L29/518
摘要： A gate dielectric can be formed by depositing a first silicon oxide material by a first atomic layer deposition process. The thickness of the first silicon oxide material is selected to correspond to at least 10 deposition cycles of the first atomic layer deposition process. The first silicon oxide material is converted into a first silicon oxynitride material by a first plasma nitridation process. A second silicon oxide material is subsequently deposited by a second atomic layer deposition process. The second silicon oxide material is converted into a second silicon oxynitride material by a second plasma nitridation process. Multiple repetitions of the atomic layer deposition process and the plasma nitridation process provides a silicon oxynitride material having a ratio of nitrogen atoms to oxygen atoms greater than 1/3, which can be advantageously employed to reduce the leakage current through a gate dielectric.
摘要翻译： 可以通过利用第一原子层沉积工艺沉积第一氧化硅材料来形成栅极电介质。 选择第一氧化硅材料的厚度以对应于第一原子层沉积工艺的至少10个沉积循环。 通过第一等离子体氮化工艺将第一氧化硅材料转化为第一氮氧化硅材料。 随后通过第二原子层沉积工艺沉积第二氧化硅材料。 通过第二等离子体氮化处理将第二氧化硅材料转化为第二氮氧化硅材料。 原子层沉积工艺和等离子体氮化处理的多次重复提供氮氮原子与氧原子的比率大于1/3的氮氧化硅材料，其可以有利地用于减少通过栅极电介质的漏电流。
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