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    Fabrication of multi threshold-voltage devices
    1.
    发明授权
    Fabrication of multi threshold-voltage devices 有权

    公开(公告)号：US10020202B2

    公开(公告)日：2018-07-10

    申请号：US15099641

    申请日：2016-04-15

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Donghun Kang ,  Balaji Kannan ,  Jinping Liu

    IPC分类号： H01L21/308 ,  H01L27/092 ,  H01L21/3065 ,  H01L21/285 ,  H01L21/306

    CPC分类号： H01L21/3085 ,  H01L21/28556 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/092

    摘要： A method of fabricating multi Vth devices and the resulting device are disclosed. Embodiments include forming a high-k dielectric layer over a substrate; forming a first TiN layer, a first barrier layer, a second TiN layer, a second barrier layer, and a third TiN layer consecutively over the high-k dielectric layer; forming a first masking layer over the third TiN layer in a first region; removing the third TiN layer in second and third regions, exposing the second barrier layer in the second and third regions; removing the first masking layer; removing the exposed second barrier layer; forming a second masking layer over the third TiN layer in the first region and the second TiN layer in the second region; removing the second TiN layer in the third region, exposing the first barrier layer in the third region; removing the second masking layer; and removing the exposed first barrier layer.

    METHOD OF FORMING GATE STRUCTURE WITH UNDERCUT REGION AND RESULTING DEVICE
    4.
    发明申请
    METHOD OF FORMING GATE STRUCTURE WITH UNDERCUT REGION AND RESULTING DEVICE 审中-公开

    公开(公告)号：US20200091005A1

    公开(公告)日：2020-03-19

    申请号：US16134708

    申请日：2018-09-18

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Qun Gao ,  Balaji Kannan ,  Shesh Mani Pandey ,  Haiting Wang

    IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/66

    摘要： A method of forming a gate structure with an undercut region includes, among other things, forming a plurality of fins above a substrate and an isolation structure above the substrate and between the plurality of fins, forming a placeholder gate structure above the plurality of fins in a first region and above the isolation structure in a second region, selectively removing a portion of the placeholder structure in the second region to define an undercut recess, forming a spacer structure adjacent the sacrificial gate structure, forming a dielectric layer adjacent the spacer structure and in the undercut recess, removing remaining portions of the placeholder gate structure to define a gate cavity, and forming a replacement gate structure in the gate cavity.

    Method of forming gate structure with undercut region and resulting device
    6.
    发明授权
    Method of forming gate structure with undercut region and resulting device 有权

    公开(公告)号：US10727133B2

    公开(公告)日：2020-07-28

    申请号：US16134708

    申请日：2018-09-18

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Qun Gao ,  Balaji Kannan ,  Shesh Mani Pandey ,  Haiting Wang

    IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L27/088

    摘要： A method of forming a gate structure with an undercut region includes, among other things, forming a plurality of fins above a substrate and an isolation structure above the substrate and between the plurality of fins, forming a placeholder gate structure above the plurality of fins in a first region and above the isolation structure in a second region, selectively removing a portion of the placeholder structure in the second region to define an undercut recess, forming a spacer structure adjacent the sacrificial gate structure, forming a dielectric layer adjacent the spacer structure and in the undercut recess, removing remaining portions of the placeholder gate structure to define a gate cavity, and forming a replacement gate structure in the gate cavity.

    FIELD EFFECT TRANSISTORS HAVING MULTIPLE EFFECTIVE WORK FUNCTIONS
    10.
    发明申请
    FIELD EFFECT TRANSISTORS HAVING MULTIPLE EFFECTIVE WORK FUNCTIONS 有权
    具有多种有效工作功能的场效应晶体管

    公开(公告)号：US20170047255A1

    公开(公告)日：2017-02-16

    申请号：US15338894

    申请日：2016-10-31

    申请人： GLOBALFOUNDRIES INC.

    发明人： Takashi Ando ,  Min Dai ,  Balaji Kannan ,  Siddarth A. Krishnan ,  Unoh Kwon

    IPC分类号： H01L21/8234 ,  H01L21/324 ,  H01L21/8238

    CPC分类号： H01L21/823412 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/785

    摘要： Selective deposition of a silicon-germanium surface layer on semiconductor surfaces can be employed to provide two types of channel regions for field effect transistors. Anneal of an adjustment oxide material on a stack of a silicon-based gate dielectric and a high dielectric constant (high-k) gate dielectric can be employed to form an interfacial adjustment oxide layer contacting a subset of channel regions. Oxygen deficiency can be induced in portions of the high-k dielectric layer overlying the interfacial adjustment oxide layer by deposition of a first work function metallic material layer and a capping layer and a subsequent anneal. Oxygen deficiency can be selectively removed by physically exposing portions of the high-k dielectric layer. A second work function metallic material layer and a gate conductor layer can be deposited and planarized to form gate electrodes that provide multiple effective work functions.

    摘要翻译： 硅 - 锗表面层在半导体表面上的选择性沉积可用于为场效应晶体管提供两种类型的沟道区。 在硅基栅极电介质和高介电常数（高k）栅极电介质的堆叠上的调整氧化物材料的退火可以用于形成接触通道区域子集的界面调整氧化物层。 通过沉积第一功函数金属材料层和封盖层和随后的退火，可以在覆盖界面调整氧化物层的高k电介质层的部分中诱导氧缺乏。 可以通过物理暴露高k电介质层的部分来选择性地去除氧缺乏。 可以将第二功函数金属材料层和栅极导体层沉积并平坦化以形成提供多个有效功函数的栅电极。