公开(公告)号：US20170040450A1

公开(公告)日：2017-02-09

申请号：US14816337

申请日：2015-08-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Sven Beyer ,  Tom Hasche ,  Jan Hoentschel

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/06 ,  H01L27/12 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/66537 ,  H01L21/743 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/7838 ,  H01L29/7843

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a method of forming a semiconductor device, the method including providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming a gate structure on the active semiconductor layer in an active region of the SOI substrate, partially exposing the base substrate for forming at least one bulk exposed region after the gate structure is formed, and forming a contact structure for contacting the at least one bulk exposed region.

Abstract translation: 本公开根据一些说明性实施例提供了一种形成半导体器件的方法，所述方法包括提供SOI衬底，所述SOI衬底具有设置在掩埋绝缘材料层上的有源半导体层，所述有源半导体层又形成在基底衬底材料 在所述SOI衬底的有源区中的所述有源半导体层上形成栅极结构，在所述栅极结构形成之后，部分地露出所述基底以形成至少一个本体暴露区域，以及形成用于使所述至少一个 体积暴露区域。

公开(公告)号：US09608112B2

公开(公告)日：2017-03-28

申请号：US14816337

申请日：2015-08-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Sven Beyer ,  Tom Hasche ,  Jan Hoentschel

IPC: H01L27/01 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L27/06 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/66537 ,  H01L21/743 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/7838 ,  H01L29/7843

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a method of forming a semiconductor device, the method including providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming a gate structure on the active semiconductor layer in an active region of the SOI substrate, partially exposing the base substrate for forming at least one bulk exposed region after the gate structure is formed, and forming a contact structure for contacting the at least one bulk exposed region.

公开(公告)号：US09040405B2

公开(公告)日：2015-05-26

申请号：US14043181

申请日：2013-10-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tom Hasche ,  Sven Beyer ,  Gerhard Lembach ,  Alexander Ebermann

IPC: H01L21/3205 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L21/28123 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/823437 ,  H01L21/823468 ,  Y10S438/942 ,  Y10S438/947

Abstract: A method of forming a semiconductor device including forming a dielectric material layer on a semiconductor layer, forming a gate electrode material layer on the dielectric material layer, forming mask features on the gate electrode material layer, forming a spacer layer on and at sidewalls of the mask features and on the gate electrode material layer between the mask features, removing the spacer layer from the gate electrode material layer between the mask features, and etching the gate electrode material layer and dielectric material layer using the hard mask features as an etch mask to obtain gate electrode structures. A semiconductor device including first and second gate electrode structures, each covered by a cap layer that comprises a mask material surrounded at the sidewalls thereof by a spacer material different from the mask material, and the distance between the first and second electrode structures is at most 100 nm.

Abstract translation: 一种形成半导体器件的方法，包括在半导体层上形成电介质材料层，在电介质材料层上形成栅电极材料层，在栅电极材料层上形成掩模特征，在栅电极材料层的侧壁上形成间隔层 掩模特征，并且在掩模特征之间的栅电极材料层上，在掩模特征之间从栅电极材料层移除间隔层，并使用硬掩模特征作为蚀刻掩模蚀刻栅电极材料层和电介质材料层， 获得栅电极结构。 一种半导体器件，包括第一和第二栅极电极结构，每个覆盖层包括掩模材料，该掩模材料在其侧壁处被不同于掩模材料的隔离材料包围，并且第一和第二电极结构之间的距离最多为 100nm。