公开(公告)号：US09548312B1

公开(公告)日：2017-01-17

申请号：US14937041

申请日：2015-11-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sven Beyer ,  Alexander Ebermann ,  Martin Schulze

IPC: H01L21/4763 ,  H01L27/115 ,  H01L21/28

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L27/11536 ,  H01L27/11539

Abstract: A method includes providing a semiconductor structure including a nonvolatile memory cell element and one or more electrically insulating layers covering the nonvolatile memory cell element. The nonvolatile memory cell element includes a source region, a channel region, a drain region and a floating gate over at least a first portion of the channel region. A first opening is formed in the electrically insulating layers over the floating gate, a control gate insulation layer is deposited, and a second opening is formed in the electrically insulating layers over the drain region. The first opening and the second opening are filled with an electrically conductive material. The electrically conductive material in the first opening provides a control gate of the nonvolatile memory cell element and the electrically conductive material in the second opening provides an electrical contact to the drain region.

Abstract translation: 一种方法包括提供包括非易失性存储单元元件和覆盖非易失性存储单元元件的一个或多个电绝缘层的半导体结构。 非易失性存储单元元件包括在沟道区的至少第一部分上的源极区，沟道区，漏极区和浮置栅极。 在浮置栅极上的电绝缘层中形成第一开口，沉积控制栅极绝缘层，并且在漏极区域上的电绝缘层中形成第二开口。 第一开口和第二开口填充有导电材料。 第一开口中的导电材料提供非易失性存储单元元件的控制栅极，并且第二开口中的导电材料提供与漏极区域的电接触。

公开(公告)号：US09123827B2

公开(公告)日：2015-09-01

申请号：US14153502

申请日：2014-01-13

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann ,  Carsten Grass

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/324 ,  H01L21/283 ,  H01L21/02

CPC classification number: H01L21/823835 ,  H01L21/02595 ,  H01L21/28097 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31144 ,  H01L21/324 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

Abstract: A method for fabricating an integrated circuit includes providing a semiconductor substrate including a gate electrode structure thereon and sidewall spacers along sidewalls of the gate electrode structure to a first height along the sidewalls, forming a planarizing carbon-based polymer layer over the gate electrode structure and over the sidewall spacers, and etching a portion of the optical planarization layer to expose a top portion the gate electrode structure. Further, the method includes etching an upper portion of the sidewall spacers selective to the gate electrode structure so as to expose the sidewalls of the upper portion of the gate electrode structure and depositing a silicide-forming material over the top portion of the gate electrode structure and the sidewalls of the upper portion of the gate electrode structure. Still further, the method includes annealing the silicide-forming material.

Abstract translation: 一种用于制造集成电路的方法包括：在其上提供包括栅电极结构的半导体衬底和沿着所述栅电极结构的侧壁的侧壁间隔物，沿着所述侧壁形成第一高度，在所述栅电极结构上方形成平坦化碳基聚合物层，以及 并且蚀刻光学平坦化层的一部分以暴露栅电极结构的顶部。 此外，该方法包括蚀刻侧壁间隔物的上部，其选择性地选择栅电极结构，以便露出栅极电极结构的上部的侧壁并在栅电极结构的顶部上沉积硅化物形成材料 以及栅电极结构的上部的侧壁。 此外，该方法包括退火硅化物形成材料。

公开(公告)号：US20150200142A1

公开(公告)日：2015-07-16

申请号：US14153502

申请日：2014-01-13

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann ,  Carsten Grass

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L21/283 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L21/823835 ,  H01L21/02595 ,  H01L21/28097 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31144 ,  H01L21/324 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

Abstract: A method for fabricating an integrated circuit includes providing a semiconductor substrate including a gate electrode structure thereon and sidewall spacers along sidewalls of the gate electrode structure to a first height along the sidewalls, forming a planarizing carbon-based polymer layer over the gate electrode structure and over the sidewall spacers, and etching a portion of the optical planarization layer to expose a top portion the gate electrode structure. Further, the method includes etching an upper portion of the sidewall spacers selective to the gate electrode structure so as to expose the sidewalls of the upper portion of the gate electrode structure and depositing a silicide-forming material over the top portion of the gate electrode structure and the sidewalls of the upper portion of the gate electrode structure. Still further, the method includes annealing the silicide-forming material.

Abstract translation: 一种用于制造集成电路的方法包括：在其上提供包括栅电极结构的半导体衬底和沿着所述栅电极结构的侧壁的侧壁间隔物，沿着所述侧壁形成第一高度，在所述栅电极结构上方形成平坦化碳基聚合物层，以及 并且蚀刻光学平坦化层的一部分以暴露栅电极结构的顶部。 此外，该方法包括蚀刻侧壁间隔物的上部，其选择性地选择栅电极结构，以便露出栅极电极结构的上部的侧壁并在栅电极结构的顶部上沉积硅化物形成材料 以及栅电极结构的上部的侧壁。 此外，该方法包括退火硅化物形成材料。

公开(公告)号：US09040405B2

公开(公告)日：2015-05-26

申请号：US14043181

申请日：2013-10-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tom Hasche ,  Sven Beyer ,  Gerhard Lembach ,  Alexander Ebermann

IPC: H01L21/3205 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L21/28123 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/823437 ,  H01L21/823468 ,  Y10S438/942 ,  Y10S438/947

Abstract: A method of forming a semiconductor device including forming a dielectric material layer on a semiconductor layer, forming a gate electrode material layer on the dielectric material layer, forming mask features on the gate electrode material layer, forming a spacer layer on and at sidewalls of the mask features and on the gate electrode material layer between the mask features, removing the spacer layer from the gate electrode material layer between the mask features, and etching the gate electrode material layer and dielectric material layer using the hard mask features as an etch mask to obtain gate electrode structures. A semiconductor device including first and second gate electrode structures, each covered by a cap layer that comprises a mask material surrounded at the sidewalls thereof by a spacer material different from the mask material, and the distance between the first and second electrode structures is at most 100 nm.

Abstract translation: 一种形成半导体器件的方法，包括在半导体层上形成电介质材料层，在电介质材料层上形成栅电极材料层，在栅电极材料层上形成掩模特征，在栅电极材料层的侧壁上形成间隔层 掩模特征，并且在掩模特征之间的栅电极材料层上，在掩模特征之间从栅电极材料层移除间隔层，并使用硬掩模特征作为蚀刻掩模蚀刻栅电极材料层和电介质材料层， 获得栅电极结构。 一种半导体器件，包括第一和第二栅极电极结构，每个覆盖层包括掩模材料，该掩模材料在其侧壁处被不同于掩模材料的隔离材料包围，并且第一和第二电极结构之间的距离最多为 100nm。

公开(公告)号：US20180012877A1

公开(公告)日：2018-01-11

申请号：US15713064

申请日：2017-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann

IPC: H01L25/16 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L25/167 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/16 ,  H01L24/83 ,  H01L25/043 ,  H01L2224/16146 ,  H01L2224/818 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/12044

Abstract: A method includes forming a stack of semiconductor die. The stack includes a first semiconductor die, a second semiconductor die and a third semiconductor die. The first semiconductor die is stacked above the second semiconductor die and the third semiconductor die is stacked above the first semiconductor die. A first optical transmitter and a first optical receiver are provided in the first semiconductor die, a second optical transmitter is provided in the second semiconductor die, and a second optical receiver is provided in the third semiconductor die. A first optical signal is transmitted from the first optical transmitter in the first semiconductor die to the second optical receiver in the third semiconductor die. A second optical signal is transmitted from the second optical transmitter in the second semiconductor die to the first optical receiver in the first semiconductor die.

公开(公告)号：US09806067B2

公开(公告)日：2017-10-31

申请号：US14803466

申请日：2015-07-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann

IPC: H01L25/16 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L25/167 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/16 ,  H01L24/83 ,  H01L25/043 ,  H01L2224/16146 ,  H01L2224/818 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/12044

Abstract: A semiconductor die is provided with an optical transmitter configured to transmit an optical signal to another die and an optical receiver configured to receive an optical signal from another die. Furthermore, a method of forming a semiconductor device is provided including forming a first semiconductor die with the steps of providing a semiconductor substrate, forming a transistor device at least partially over the semiconductor substrate, forming an optical receiver one of at least partially over and at least partially in the semiconductor substrate, forming a metallization layer over the transistor device, and forming an optical transmitter one of at least partially over the metallization layer and at least partially in the metallization layer.

公开(公告)号：US09698179B2

公开(公告)日：2017-07-04

申请号：US15042547

申请日：2016-02-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann

IPC: H01L27/13 ,  H01L49/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L27/13 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1207 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/66477 ,  H01L29/78

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a capacitor structure comprising an active region formed in a semiconductor substrate, a MOSFET device comprising source and drain regions formed in the active region and a gate electrode formed above the active region, and a first electrode and a second electrode formed in a metallization layer above the MOSFET device, wherein the first electrode is electrically connected with the source and drain regions via respective source and drain contacts and the second electrode is electrically connected with the gate electrode via a gate contact.

公开(公告)号：US20150200140A1

公开(公告)日：2015-07-16

申请号：US14153521

申请日：2014-01-13

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Sven Beyer ,  Alexander Ebermann ,  Carsten Grass ,  Jan Hoentschel

IPC: H01L21/8234 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/3065 ,  H01L21/28 ,  H01L21/027 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/02172 ,  H01L21/0275 ,  H01L21/28123 ,  H01L21/28176 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/823437 ,  H01L21/845

Abstract: A method for fabricating an integrated circuit includes providing a semiconductor substrate with a pad layer overlying the semiconductor substrate and a photoresist layer overlying the pad layer, exposing the photoresist layer to a split laser beam to form a plurality of parallel linear void regions in the photoresist layer, and etching the pad layer and the semiconductor substrate beneath the plurality of parallel linear void regions to form a plurality of extended parallel linear void regions. The method further includes depositing a first dielectric material over the semiconductor substrate, patterning a photoresist material over the semiconductor substrate to cover a portion of the semiconductor substrate, and etching portions of the pad layer, the first dielectric material, and the semiconductor substrate. Still further, the method includes depositing a second dielectric material into the second void regions.

Abstract translation: 一种用于制造集成电路的方法包括：提供具有覆盖在半导体衬底上的衬垫层的半导体衬底和覆盖衬垫层的光致抗蚀剂层，将光致抗蚀剂层暴露于分裂激光束以在光刻胶中形成多个平行的线性空隙区域 并且在所述多个平行线性空隙区域下方蚀刻所述衬垫层和所述半导体衬底，以形成多个延伸的平行线性空隙区域。 该方法还包括在半导体衬底上沉积第一介电材料，在半导体衬底上图案化光致抗蚀剂材料以覆盖半导体衬底的一部分，以及蚀刻衬垫层，第一电介质材料和半导体衬底的部分。 此外，该方法包括将第二电介质材料沉积到第二空隙区域中。

公开(公告)号：US10283490B2

公开(公告)日：2019-05-07

申请号：US15713064

申请日：2017-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann

IPC: H01L25/16 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L25/04

Abstract: A method includes forming a stack of semiconductor die. The stack includes a first semiconductor die, a second semiconductor die and a third semiconductor die. The first semiconductor die is stacked above the second semiconductor die and the third semiconductor die is stacked above the first semiconductor die. A first optical transmitter and a first optical receiver are provided in the first semiconductor die, a second optical transmitter is provided in the second semiconductor die, and a second optical receiver is provided in the third semiconductor die. A first optical signal is transmitted from the first optical transmitter in the first semiconductor die to the second optical receiver in the third semiconductor die. A second optical signal is transmitted from the second optical transmitter in the second semiconductor die to the first optical receiver in the first semiconductor die.

公开(公告)号：US20170040354A1

公开(公告)日：2017-02-09

申请号：US15042547

申请日：2016-02-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann

IPC: H01L27/13 ,  H01L29/78 ,  H01L21/84 ,  H01L29/06 ,  H01L27/12 ,  H01L49/02 ,  H01L29/66

CPC classification number: H01L27/13 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1207 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/66477 ,  H01L29/78

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a capacitor structure comprising an active region formed in a semiconductor substrate, a MOSFET device comprising source and drain regions formed in the active region and a gate electrode formed above the active region, and a first electrode and a second electrode formed in a metallization layer above the MOSFET device, wherein the first electrode is electrically connected with the source and drain regions via respective source and drain contacts and the second electrode is electrically connected with the gate electrode via a gate contact.

Abstract translation: 根据一些示例性实施例，本公开提供包括形成在半导体衬底中的有源区的电容器结构，包括形成在有源区中的源区和漏区以及形成在有源区上方的栅极的MOSFET器件，以及 第一电极和形成在MOSFET器件上方的金属化层中的第二电极，其中第一电极经由相应的源极和漏极触点与源极和漏极区域电连接，并且第二电极经由栅极触点与栅电极电连接 。