公开(公告)号：US20150377956A1

公开(公告)日：2015-12-31

申请号：US14314693

申请日：2014-06-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： William MCMAHON ,  Andreas KERBER ,  Luigi PANTISANO ,  Suresh UPPAL

IPC: G01R31/28

CPC classification number: G01R31/2875 ,  G01R31/2879

Abstract: A methodology for inline characterization and temperature profiling that enables parallel measurement of device characteristics at multiple temperatures and the resulting device are disclosed. Embodiments may include calibrating a first device under test (DUT) with respect to at least one heating structure in a metal layer of an integrated circuit (IC), applying a heater voltage to the at least one heating structure, and measuring at least one characteristic of the first DUT at a first temperature corresponding to the heater voltage.

Abstract translation: 公开了一种在线表征和温度分析的方法，其可以在多个温度下平行测量器件特性，并且得到所得到的器件。 实施例可以包括相对于集成电路（IC）的金属层中的至少一个加热结构校准被测试的第一器件（DUT），向至少一个加热结构施加加热器电压，以及测量至少一个特性 在与加热器电压对应的第一温度下的第一DUT。

公开(公告)号：US20160284421A1

公开(公告)日：2016-09-29

申请号：US14664959

申请日：2015-03-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vivek JOSHI ,  Sriram BALASUBRAMANIAN ,  CHAD WEINTRAUB ,  Yoann Mamy RANDRIAMIHAJA ,  William MCMAHON

IPC: G11C29/04 ,  G11C11/419

CPC classification number: G11C29/04 ,  G11C11/412 ,  G11C11/419 ,  G11C29/56008

Abstract: A method and an apparatus for identifying non-intrinsic defect bits from a population of failing bits for failure analysis to characterize the extrinsic failure mechanisms is provided. Embodiments include performing a failure mode test on a bank of a memory array at different low VDD; determining optimal bank size to observe plateaus of fail counts; determining fail counts of the bank at each different low VDD; determining a plateau of the fail counts; determining whether the plateau represents extrinsic bits of the bank; and submitting the extrinsic bits for root cause analysis.

Abstract translation: 提供了一种用于从用于故障分析的故障位群体中识别非本征缺陷位以表征外在故障机制的方法和装置。 实施例包括在不同的低VDD下对存储器阵列进行故障模式测试; 确定最佳银行规模以观察失败计数的平稳度; 在每个不同的低VDD处确定存储体的故障计数; 确定失败计数的高原; 确定平台是否代表银行的外在位; 并提交根本原因分析的外在位。

公开(公告)号：US20160054383A1

公开(公告)日：2016-02-25

申请号：US14462643

申请日：2014-08-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anil KUMAR ,  Suresh UPPAL ,  Manjunatha PRABHU ,  William MCMAHON

IPC: G01R31/28 ,  G01R31/26

CPC classification number: G01R31/2884 ,  G01R31/2601 ,  G01R31/2644 ,  H01L22/34

Abstract: There is set forth herein a semiconductor structure including a plurality of test devices, the plurality of test devices including a first test device and a second test device. A semiconductor structure can also include a waveform generating circuit, the waveform generating circuit configured for application of a first stress signal waveform having a first duty cycle to the first test device, and a second stress signal waveform having a second duty cycle to the second test device. A semiconductor structure can include a selection circuit associated with each of the first test device and the second test device for switching between a stress cycle and a sensing cycle.

Abstract translation: 这里提出了包括多个测试装置的半导体结构，所述多个测试装置包括第一测试装置和第二测试装置。 半导体结构还可以包括波形发生电路，波形发生电路被配置为将第一应力信号波形具有第一占空比施加到第一测试装置，第二应力信号波形具有第二占空比到第二测试 设备。 半导体结构可以包括与第一测试装置和第二测试装置中的每一个相关联的选择电路，用于在应力循环和感测周期之间切换。