公开(公告)号：US09006906B2

公开(公告)日：2015-04-14

申请号：US14312077

申请日：2014-06-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dmytro Chumakov ,  Wolfgang Buchholtz ,  Petra Hetzer

IPC: H01L23/48 ,  H01L23/52 ,  H01L27/108 ,  B82Y10/00 ,  H01L49/02

CPC classification number: H01L27/1082 ,  B82Y10/00 ,  H01L27/10852 ,  H01L28/90

Abstract: A capacitor is formed in nano channels in a conductive body. Embodiments include forming a source contact through a first inter layer dielectric (ILD), forming a conductive body on the first ILD, forming a second ILD on the conductive body, forming drain and gate contacts through the second ILD, conductive body, and first ILD, forming nano channels in the conductive body, forming an insulating layer in the channels, and metalizing the channels. An embodiment includes forming the nano channels by forming a mask on the second ILD, the mask having features with a pitch of 50 nanometers (nm) to 100 nm, etching the second ILD through the mask, etching the conductive body through the mask to a depth of 80% to 90% of the thickness of the conductive body, and removing the mask.

Abstract translation: 在导电体中的纳米通道中形成电容器。 实施例包括通过第一层间电介质（ILD）形成源极接触，在第一ILD上形成导电体，在导电体上形成第二ILD，通过第二ILD，导电体和第一ILD形成漏极和栅极接触 在导电体中形成纳米通道，在通道中形成绝缘层，并使通道金属化。 一个实施方案包括通过在第二ILD上形成掩模形成纳米通道，该掩模具有50纳米（nm）至100nm的间距的特征，通过掩模蚀刻第二ILD，通过掩模将导电体蚀刻到 深度为导电体的厚度的80％至90％，并且去除掩模。

公开(公告)号：US20150333057A1

公开(公告)日：2015-11-19

申请号：US14276515

申请日：2014-05-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Andreas Kurz ,  Sven Beyer ,  Wolfgang Buchholtz

IPC: H01L27/07 ,  H01L49/02

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/308 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0629 ,  H01L27/0738 ,  H01L28/20 ,  H01L29/66545

Abstract: The present disclosure relates to a semiconductor structure comprising a resistor, at least part of the resistor forming a meandering shape in a vertical direction with respect to a substrate of the semiconductor structure. The disclosure further relates to a semiconductor manufacturing process comprising a step for realizing at least one first fin, and a step for realizing a resistor comprising a meandering shape in a vertical direction based on the at least one first fin.

Abstract translation: 本公开涉及包括电阻器的半导体结构，所述电阻器的至少一部分相对于半导体结构的衬底在垂直方向上形成曲折形状。 本发明还涉及包括用于实现至少一个第一鳍的步骤的半导体制造工艺，以及基于至少一个第一鳍实现在垂直方向上包括曲折形状的电阻的步骤。

公开(公告)号：US20160141393A1

公开(公告)日：2016-05-19

申请号：US15003370

申请日：2016-01-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Andreas Kurz ,  Sven Beyer ,  Wolfgang Buchholtz

IPC: H01L29/66 ,  H01L21/308 ,  H01L49/02 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/308 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0629 ,  H01L27/0738 ,  H01L28/20 ,  H01L29/66545

Abstract: A method includes forming a plurality of fins in a semiconductor substrate using a common patterning process. A conductive layer is formed above the plurality of fins. A mask is formed above the conductive layer. The conductive layer is etched using the mask to define trenches in the conductive layer. A first insulating layer is formed above the conductive layer and in the trenches. First and second contacts are formed connected to respective ends of the conductive layer.

Abstract translation: 一种方法包括使用共同的图案化工艺在半导体衬底中形成多个翅片。 在多个翅片上方形成导电层。 在导电层上方形成掩模。 使用掩模蚀刻导电层以在导电层中限定沟槽。 第一绝缘层形成在导电层上方和沟槽中。 第一和第二触点形成为连接到导电层的相应末端。