公开(公告)号：US09899319B2

公开(公告)日：2018-02-20

申请号：US15428604

申请日：2017-02-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andreas Kurz ,  Andrei Sidelnicov

IPC: H01L23/525 ,  H01L29/08 ,  H01L29/06 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L23/5256 ,  H01L21/02532 ,  H01L21/76264 ,  H01L21/84 ,  H01L23/53209 ,  H01L27/1203 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/41783 ,  H01L29/66515 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7838

Abstract: A semiconductor device with a semiconductor-on-insulator (SOI) structure is provided including an insulating layer and a semiconductor layer formed on the insulating layer and a fuse. The fuse includes a first at least partially silicided raised semiconductor region with a first silicided portion and, adjacent to the first at least partially silicided raised semiconductor region, a second at least partially silicided raised semiconductor region with a second silicided portion. The second silicided portion is formed in direct physical contact with the first silicided portion.

公开(公告)号：US20160204065A1

公开(公告)日：2016-07-14

申请号：US15077378

申请日：2016-03-22

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ricardo Mikalo ,  Andreas Kurz ,  Alexandru Romanescu

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  G11C17/16 ,  H01L23/345 ,  H01L23/62 ,  H01L27/1026 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits including electronic fuse structures are disclosed. In some examples, the electronic fuse structure includes a fuse part and first and second pre-heating lines positioned generally parallel to and co-planar with the fuse part, and electrically connected with the fuse part. The electronic fuse structure also includes a cathode physically and electrically connected to the first pre-heating line and an anode physically and electrically connected to the second pre-heating line.

公开(公告)号：US08785300B2

公开(公告)日：2014-07-22

申请号：US13942800

申请日：2013-07-16

Applicant: GlobalFoundries Inc.

Inventor： Andreas Kurz ,  Jens Poppe

IPC: H01L21/326 ,  H01L21/479

CPC classification number: H01L23/5252 ,  H01L21/76886 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An approach is provided for semiconductor devices including an anti-fuse structure. The semiconductor device includes a first metallization layer including a first portion of a first electrode and a second electrode, the second electrode being formed in a substantially axial plane surrounding the first portion of the first electrode, with a dielectric material in between the two electrodes. An ILD is formed over the first metallization layer, a second metallization layer including a second portion of the first electrode is formed over the ILD, and at least one via is formed through the ILD, electrically connecting the first and second portions of the first electrode. Breakdown of the dielectric material is configured to enable an operating current to flow between the second electrode and the first electrode in a programmed state of the anti-fuse structure.

Abstract translation: 为包括反熔丝结构的半导体器件提供了一种方法。 半导体器件包括第一金属化层，其包括第一电极和第二电极的第一部分，第二电极形成在围绕第一电极的第一部分的大致轴向平面中，在两个电极之间具有介电材料。 在第一金属化层上形成ILD，在ILD上形成包括第一电极的第二部分的第二金属化层，并且通过ILD形成至少一个通孔，电连接第一电极的第一和第二部分 。 介电材料的击穿被配置为使得工作电流能够在反熔丝结构的编程状态下在第二电极和第一电极之间流动。

公开(公告)号：US20150333057A1

公开(公告)日：2015-11-19

申请号：US14276515

申请日：2014-05-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Andreas Kurz ,  Sven Beyer ,  Wolfgang Buchholtz

IPC: H01L27/07 ,  H01L49/02

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/308 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0629 ,  H01L27/0738 ,  H01L28/20 ,  H01L29/66545

Abstract: The present disclosure relates to a semiconductor structure comprising a resistor, at least part of the resistor forming a meandering shape in a vertical direction with respect to a substrate of the semiconductor structure. The disclosure further relates to a semiconductor manufacturing process comprising a step for realizing at least one first fin, and a step for realizing a resistor comprising a meandering shape in a vertical direction based on the at least one first fin.

Abstract translation: 本公开涉及包括电阻器的半导体结构，所述电阻器的至少一部分相对于半导体结构的衬底在垂直方向上形成曲折形状。 本发明还涉及包括用于实现至少一个第一鳍的步骤的半导体制造工艺，以及基于至少一个第一鳍实现在垂直方向上包括曲折形状的电阻的步骤。

公开(公告)号：US20130307114A1

公开(公告)日：2013-11-21

申请号：US13952792

申请日：2013-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jens Poppe ,  Oliver Aubel ,  Christian Hennesthal ,  Holger Pagel ,  Andreas Kurz

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  G11C17/16 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Metal fuses in semiconductor devices may be formed on the basis of additional mechanisms for obtaining superior electromigration in the fuse bodies. To this end, the compressive stress caused by the current-induced metal diffusion may be restricted or reduced in the fuse body, for instance, by providing a stress buffer region and/or by providing a dedicated metal agglomeration region. The concept may be applied to the metallization system and may also be used in the device level, when fabricating the metal fuse in combination with high-k metal gate electrode structures.

Abstract translation: 可以基于用于在保险丝体中获得优异的电迁移的附加机构来形成半导体器件中的金属熔丝。 为此，例如通过提供应力缓冲区域和/或通过提供专用的金属附聚区域，可以限制或减小由电流引起的金属扩散引起的压缩应力。 该概念可以应用于金属化系统，并且当与高k金属栅电极结构组合制造金属熔丝时也可以在器件级中使用。

公开(公告)号：US09324654B2

公开(公告)日：2016-04-26

申请号：US14459607

申请日：2014-08-14

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ricardo Mikalo ,  Andreas Kurz ,  Alexandru Romanescu

IPC: H01L23/52 ,  H01L23/525 ,  H01L27/102 ,  H01L23/62 ,  H01L27/112

CPC classification number: H01L23/5256 ,  G11C17/16 ,  H01L23/345 ,  H01L23/62 ,  H01L27/1026 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits including electronic fuse structures are disclosed. In some examples, the electronic fuse structure includes a fuse part and first and second pre-heating lines positioned generally parallel to and co-planar with the fuse part, and electrically connected with the fuse part. The electronic fuse structure also includes a cathode physically and electrically connected to the first pre-heating line and an anode physically and electrically connected to the second pre-heating line.

Abstract translation: 公开了包括电子熔断器结构的集成电路。 在一些示例中，电子熔丝结构包括熔丝部分和大致平行于并且与熔丝部分共面定位并与熔丝部分电连接的第一和第二预热线。 电子熔丝结构还包括物理地和电连接到第一预热线的阴极和物理地和电连接到第二预热线的阳极。

公开(公告)号：US20160049366A1

公开(公告)日：2016-02-18

申请号：US14459607

申请日：2014-08-14

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ricardo Mikalo ,  Andreas Kurz ,  Alexandru Romanescu

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  G11C17/16 ,  H01L23/345 ,  H01L23/62 ,  H01L27/1026 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits including electronic fuse structures are disclosed. In some examples, the electronic fuse structure includes a fuse part and first and second pre-heating lines positioned generally parallel to and co-planar with the fuse part, and electrically connected with the fuse part. The electronic fuse structure also includes a cathode physically and electrically connected to the first pre-heating line and an anode physically and electrically connected to the second pre-heating line.

Abstract translation: 公开了包括电子熔断器结构的集成电路。 在一些示例中，电子熔丝结构包括熔丝部分和大致平行于并且与熔丝部分共面定位并与熔丝部分电连接的第一和第二预热线。 电子熔丝结构还包括物理地和电连接到第一预热线的阴极和物理地和电连接到第二预热线的阳极。

公开(公告)号：US09524962B2

公开(公告)日：2016-12-20

申请号：US14136581

申请日：2013-12-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andrei Sidelnicov ,  Andreas Kurz ,  Alexandru Romanescu

IPC: H01L29/49 ,  H01L23/62 ,  H01L21/285 ,  H01L27/06 ,  H01L23/525 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L23/5256 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor device including the steps of forming an electrically programmable fuse (e-fuse) on an isolation region and a transistor on an active region of a wafer, wherein forming the transistor includes forming a dummy gate above a substrate, removing the dummy gate and forming a metal gate in place of the dummy gate, and forming the e-fuse includes forming a metal-containing layer above the isolation region, forming a semiconductor layer on the metal-containing layer during the process of forming the dummy gate and of the same material as the dummy gate, forming a hard mask layer on the semiconductor layer formed on the metal-containing layer, and forming contact openings in the hard mask layer and semiconductor layer during the process of removing the dummy gate.

Abstract translation: 一种形成半导体器件的方法，包括以下步骤：在隔离区域上形成电可编程熔丝（e-fuse）和在晶片的有源区上形成晶体管，其中形成晶体管包括在衬底上形成虚拟栅极，去除 虚拟栅极和形成金属栅极代替虚拟栅极，并且形成e熔丝包括在隔离区域上方形成含金属层，在形成虚拟栅极的过程中在含金属层上形成半导体层 栅极和与虚拟栅极相同的材料，在形成在含金属层上的半导体层上形成硬掩模层，并且在去除虚拟栅极的过程中在硬掩模层和半导体层中形成接触开口。

公开(公告)号：US08653624B2

公开(公告)日：2014-02-18

申请号：US13952792

申请日：2013-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Christian Hennesthal ,  Oliver Aubel ,  Jens Poppe ,  Holger Pagel ,  Andreas Kurz

IPC: H01L23/52

CPC classification number: H01L23/5256 ,  G11C17/16 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Metal fuses in semiconductor devices may be formed on the basis of additional mechanisms for obtaining superior electromigration in the fuse bodies. To this end, the compressive stress caused by the current-induced metal diffusion may be restricted or reduced in the fuse body, for instance, by providing a stress buffer region and/or by providing a dedicated metal agglomeration region. The concept may be applied to the metallization system and may also be used in the device level, when fabricating the metal fuse in combination with high-k metal gate electrode structures.

Abstract translation: 可以基于用于在保险丝体中获得优异的电迁移的附加机构来形成半导体器件中的金属熔丝。 为此，例如通过提供应力缓冲区域和/或通过提供专用的金属附聚区域，可以限制或减小由电流引起的金属扩散引起的压缩应力。 该概念可以应用于金属化系统，并且当与高k金属栅电极结构组合制造金属熔丝时也可以在器件级中使用。

公开(公告)号：US20170154846A1

公开(公告)日：2017-06-01

申请号：US15428604

申请日：2017-02-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andreas Kurz ,  Andrei Sidelnicov

IPC: H01L23/525 ,  H01L29/08 ,  H01L29/06 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L23/5256 ,  H01L21/02532 ,  H01L21/76264 ,  H01L21/84 ,  H01L23/53209 ,  H01L27/1203 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/41783 ,  H01L29/66515 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7838

Abstract: A semiconductor device with a semiconductor-on-insulator (SOI) structure is provided including an insulating layer and a semiconductor layer formed on the insulating layer and a fuse. The fuse includes a first at least partially silicided raised semiconductor region with a first silicided portion and, adjacent to the first at least partially silicided raised semiconductor region, a second at least partially silicided raised semiconductor region with a second silicided portion. The second silicided portion is formed in direct physical contact with the first silicided portion.