公开(公告)号：US10153211B1

公开(公告)日：2018-12-11

申请号：US15616681

申请日：2017-06-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanzhen Wang ,  Xinyuan Dou ,  Sipeng Gu

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L23/535 ,  H01L23/532

CPC classification number: H01L21/823468 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/53266 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/4983

Abstract: At least one method, apparatus and system is disclosed herein for forming a fin field effect transistor (finFET) device having a reduced breakdown voltage. The method comprises forming a first gate structure on a substrate of a semiconductor wafer in a first layer, the gate structure extending to a height of about h above the substrate. A trench is formed in the first layer adjacent the first gate structure and extends from a height of about d to the substrate. A connector is formed in the trench between the substrate and a layer of the finFET above the first layer. The process of forming the connector comprises; forming a thin film oxide on the sidewalls of the trench extending from a height below h to about d; forming a liner in the trench, extending over the substrate and on the sidewalls to about the height d over the thin film oxide and forming a layer of tungsten in the trench over the liner.

公开(公告)号：US20180358267A1

公开(公告)日：2018-12-13

申请号：US15616681

申请日：2017-06-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanzhen Wang ,  Xinyuan Dou ,  Sipeng Gu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L23/535 ,  H01L23/532

CPC classification number: H01L21/823468 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/53266 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/4983

Abstract: At least one method, apparatus and system is disclosed herein for forming a fin field effect transistor (finFET) device having a reduced breakdown voltage. The method comprises forming a first gate structure on a substrate of a semiconductor wafer in a first layer, the gate structure extending to a height of about h above the substrate. A trench is formed in the first layer adjacent the first gate structure and extends from a height of about d to the substrate. A connector is formed in the trench between the substrate and a layer of the finFET above the first layer. The process of forming the connector comprises; forming a thin film oxide on the sidewalls of the trench extending from a height below h to about d; forming a liner in the trench, extending over the substrate and on the sidewalls to about the height d over the thin film oxide and forming a layer of tungsten in the trench over the liner.

公开(公告)号：US10074732B1

公开(公告)日：2018-09-11

申请号：US15622902

申请日：2017-06-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xinyuan Dou ,  Hui Zang ,  Hong Yu ,  Yanzhen Wang

IPC: H01L29/00 ,  H01L21/8228 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/66818 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, forming first and second fins for a short channel FinFET device (“SCD”) and a long channel FinFET device (“LCD”), performing an oxidation process to form a sacrificial oxide material selectively on the channel portion of one of the first and second fins but not on the channel portion of the other of the first and second fins, removing the sacrificial oxide material from the fin on which it is formed so as to produce a reduced-size channel portion on that fin that is less than the initial size of the channel portion of the other non-oxidized fin, and forming first and second gate structures for the SCD and LCD devices.

公开(公告)号：US10580857B2

公开(公告)日：2020-03-03

申请号：US16010694

申请日：2018-06-18

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Yanzhen Wang ,  Xinyuan Dou ,  Hongliang Shen ,  Sipeng Gu

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

Abstract: A shallow trench isolation (STI) structure is formed from a conventional STI trench structure of a first dielectric material extending into the substrate. The conventional STI structure undergoes further processing: removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride spacer layer is formed above the remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses to a lever above the substrate. A nitride capping layer and another dielectric layer are disposed above the second material, thereby substantially encasing the STI structure in nitride. This provides a taller STI structure that results in a better fin profile during a subsequent fin reveal process.

公开(公告)号：US20190386100A1

公开(公告)日：2019-12-19

申请号：US16010694

申请日：2018-06-18

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Yanzhen Wang ,  Xinyuan Dou ,  Hongliang Shen ,  Sipeng Gu

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L21/02 ,  H01L29/66

Abstract: A shallow trench isolation (STI) structure is formed from a conventional STI trench structure of a first dielectric material extending into the substrate. The conventional STI structure undergoes further processing: removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride spacer layer is formed above the remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses to a lever above the substrate. A nitride capping layer and another dielectric layer are disposed above the second material, thereby substantially encasing the STI structure in nitride. This provides a taller STI structure that results in a better fin profile during a subsequent fin reveal process.

公开(公告)号：US10177151B1

公开(公告)日：2019-01-08

申请号：US15632702

申请日：2017-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanzhen Wang ,  Hui Zang ,  Bingwu Liu

IPC: H01L23/535 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66

Abstract: A method and structure for a semiconductor device that includes one or more fin-type field effect transistors (FINFETs) and single-diffusion break (SDB) type isolation regions, which are within a semiconductor fin and define the active device region(s) for the FINFET(s). Asymmetric trenches are formed in a substrate through asymmetric cuts in sacrificial fins formed on the substrate. The asymmetric cuts have relatively larger gaps between fin portions that are closest to the substrate, and deeper portions of the asymmetric trenches are relatively wider than shallower portions. Channel regions are formed in the substrate below two adjacent fins. Source/drain regions of complementary transistors are formed in the substrate on opposite sides of the channel regions. The asymmetric trenches are filled with an insulator to form a single-diffusion break between two source/drain regions of different ones of the complementary transistors. Also disclosed is a semiconductor structure formed according to the method.

公开(公告)号：US10014296B1

公开(公告)日：2018-07-03

申请号：US15487636

申请日：2017-04-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xinyuan Dou ,  Hong Yu ,  Sipeng Gu ,  Yanzhen Wang

IPC: H01L21/761 ,  H01L29/165 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/762

CPC classification number: H01L27/0886 ,  H01L21/02532 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: Disclosed is a method of forming a semiconductor structure that includes one or more fin-type field effect transistors (FINFETs) and single-diffusion break (SDB) type isolation regions that are within a semiconductor fin and that define the active device region(s) for the FINFET(s). The isolation regions are formed so that they include a semiconductor liner. The semiconductor liner ensures that, when a source/drain recess is formed immediately adjacent to the isolation region, the bottom and opposing sides of the source/drain recess will have semiconductor surfaces onto which epitaxial semiconductor material for a source/drain region is grown. As a result, the angle of the top surface of the source/drain region relative to the top surface of the semiconductor fin is minimized. Thus, the risk that a subsequently formed source/drain contact will not reach the source/drain region is also minimized. Also disclosed is a semiconductor structure formed according to the method.

公开(公告)号：US09748392B1

公开(公告)日：2017-08-29

申请号：US15053867

申请日：2016-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanzhen Wang ,  Jidong Huang ,  Hui Zang

IPC: H01L21/283 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/285 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L29/7851 ,  H01L21/28008 ,  H01L21/2855 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/785

Abstract: An angled gas cluster ion beam is used for each sidewall and top of a fin (two applications) to form work-function metal layer(s) only on the sidewalls and top of each fin.