公开(公告)号：US20200013678A1

公开(公告)日：2020-01-09

申请号：US16026130

申请日：2018-07-03

申请人： GLOBALFOUNDRIES INC.

发明人： Sipeng Gu ,  Akshey Sehgal ,  Xinyuan Dou ,  Sunil K. Singh ,  Ravi P. Srivastava ,  Haiting Wang ,  Scott H. Beasor

IPC分类号： H01L21/8234 ,  H01L29/08 ,  H01L29/423 ,  H01L23/48 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/49 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/66

摘要： This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor structure including two source/drain regions; a metal gate positioned on the semiconductor structure adjacent to and between the source/drain regions; a metal cap with a different metal composition than the metal gate and having a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm positioned on the metal gate; a first dielectric cap layer positioned above the semiconductor structure; an inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein an upper surface of the ILD has a greater height above the semiconductor structure than an upper surface of the metal gate; a second dielectric cap layer positioned on the ILD and above the metal cap; and a contact on and in electrical contact with the metal cap.

公开(公告)号：US10714380B2

公开(公告)日：2020-07-14

申请号：US16171477

申请日：2018-10-26

申请人： GLOBALFOUNDRIES INC.

发明人： Ravi P. Srivastava ,  Sipeng Gu ,  Sunil K. Singh ,  Xinyuan Dou ,  Akshey Sehgal ,  Zhiguo Sun

IPC分类号： H01L21/768 ,  H01L21/02

摘要： The present disclosure generally relates to semiconductor structures and, more particularly, to smooth sidewall structures and methods of manufacture. The method includes: forming a plurality of mandrel structures; forming a first spacer material on each of the plurality of mandrel structures; forming a second spacer material over the first spacer material; and removing the first spacer material and the plurality of mandrel structures to form a sidewall structure having a sidewall smoothness greater than the plurality of mandrel structures.

公开(公告)号：US09831098B2

公开(公告)日：2017-11-28

申请号：US14797337

申请日：2015-07-13

申请人： GLOBALFOUNDRIES, Inc.

发明人： Xinyuan Dou ,  Sukwon Hong ,  Satyajit Shinde ,  Sandeep Gaan ,  Tao Han ,  Carlos Chacon ,  Shimpei Yamaguchi

IPC分类号： H01L21/3105 ,  H01L29/423 ,  H01L29/66 ,  H01L21/762

CPC分类号： H01L21/3105 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/76229 ,  H01L29/42356 ,  H01L29/66795

摘要： Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an isolation trench between two fin structures on an integrated circuit substrate, forming a flowable film in the isolation trench using a flowable chemical vapor deposition process, and annealing the flowable film to form a silicon oxide dielectric layer in the isolation trench. The annealing is performed at a temperature of less than about 200° C. with a process gas including N2 and H2O2.

公开(公告)号：US10153211B1

公开(公告)日：2018-12-11

申请号：US15616681

申请日：2017-06-07

申请人： GLOBALFOUNDRIES INC.

发明人： Yanzhen Wang ,  Xinyuan Dou ,  Sipeng Gu

IPC分类号： H01L21/8238 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L23/535 ,  H01L23/532

CPC分类号： H01L21/823468 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/53266 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/4983

摘要： At least one method, apparatus and system is disclosed herein for forming a fin field effect transistor (finFET) device having a reduced breakdown voltage. The method comprises forming a first gate structure on a substrate of a semiconductor wafer in a first layer, the gate structure extending to a height of about h above the substrate. A trench is formed in the first layer adjacent the first gate structure and extends from a height of about d to the substrate. A connector is formed in the trench between the substrate and a layer of the finFET above the first layer. The process of forming the connector comprises; forming a thin film oxide on the sidewalls of the trench extending from a height below h to about d; forming a liner in the trench, extending over the substrate and on the sidewalls to about the height d over the thin film oxide and forming a layer of tungsten in the trench over the liner.

公开(公告)号：US10083873B1

公开(公告)日：2018-09-25

申请号：US15613981

申请日：2017-06-05

申请人： GLOBALFOUNDRIES INC.

发明人： Xing Zhang ,  Xinyuan Dou ,  Hong Yu ,  Zhenyu Hu

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/10

CPC分类号： H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/1033 ,  H01L29/66795 ,  H01L29/785

摘要： The present disclosure relates to semiconductor structures and, more particularly, to semiconductor structures with uniform gate heights and methods of manufacture. The structure includes: short channel devices in a first area of an integrated circuit die; and long channel devices in a second area of the integrated circuit die. The long channel devices have a same gate height as the short channel devices.

公开(公告)号：US20170018452A1

公开(公告)日：2017-01-19

申请号：US14797337

申请日：2015-07-13

申请人： GLOBALFOUNDRIES, Inc.

发明人： Xinyuan Dou ,  Sukwon Hong ,  Satyajit Shinde ,  Sandeep Gaan ,  Tao Han ,  Carlos Chacon ,  Shimpei Yamaguchi

IPC分类号： H01L21/762 ,  H01L29/66 ,  H01L21/3105 ,  H01L29/423

CPC分类号： H01L21/3105 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/76229 ,  H01L29/42356 ,  H01L29/66795

摘要： Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an isolation trench between two fin structures on an integrated circuit substrate, forming a flowable film in the isolation trench using a flowable chemical vapor deposition process, and annealing the flowable film to form a silicon oxide dielectric layer in the isolation trench. The annealing is performed at a temperature of less than about 200° C. with a process gas including N2 and H2O2.

摘要翻译： 提供了制造集成电路的方法。 在一个示例中，制造集成电路的方法包括在集成电路基板上的两个鳍结构之间形成隔离沟槽，使用可流动的化学气相沉积工艺在隔离沟槽中形成可流动的膜，并对可流动薄膜进行退火以形成 隔离沟槽中的氧化硅介电层。 使用包括N 2和H 2 O 2的工艺气体在小于约200℃的温度下进行退火。

公开(公告)号：US10910276B1

公开(公告)日：2021-02-02

申请号：US16589789

申请日：2019-10-01

申请人： GLOBALFOUNDRIES INC.

发明人： Yongjun Shi ,  Xinyuan Dou ,  Chun Yu Wong ,  Hongliang Shen ,  Baofu Zhu

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L21/762 ,  H01L27/092 ,  H01L29/78

摘要： A structure, an STI structure and a related method are disclosed. The structure may include an active region extending from a substrate; a gate extending over the active region; and a source/drain region in the active region, and an STI structure. The STI structure includes a liner and a fill layer on the liner along the opposed longitudinal sides of a lower portion of the active region, and the fill layer along the opposed ends of the active region. The liner may include a tensile stress-inducing liner that imparts a transverse-to-length tensile stress in at least a lower portion of the active region but not lengthwise. The liner can be applied in an n-FET region and/or a p-FET region to improve performance.

公开(公告)号：US20180358267A1

公开(公告)日：2018-12-13

申请号：US15616681

申请日：2017-06-07

申请人： GLOBALFOUNDRIES INC.

发明人： Yanzhen Wang ,  Xinyuan Dou ,  Sipeng Gu

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L23/535 ,  H01L23/532

CPC分类号： H01L21/823468 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/53266 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/4983

摘要： At least one method, apparatus and system is disclosed herein for forming a fin field effect transistor (finFET) device having a reduced breakdown voltage. The method comprises forming a first gate structure on a substrate of a semiconductor wafer in a first layer, the gate structure extending to a height of about h above the substrate. A trench is formed in the first layer adjacent the first gate structure and extends from a height of about d to the substrate. A connector is formed in the trench between the substrate and a layer of the finFET above the first layer. The process of forming the connector comprises; forming a thin film oxide on the sidewalls of the trench extending from a height below h to about d; forming a liner in the trench, extending over the substrate and on the sidewalls to about the height d over the thin film oxide and forming a layer of tungsten in the trench over the liner.

公开(公告)号：US10074732B1

公开(公告)日：2018-09-11

申请号：US15622902

申请日：2017-06-14

申请人： GLOBALFOUNDRIES Inc.

发明人： Xinyuan Dou ,  Hui Zang ,  Hong Yu ,  Yanzhen Wang

IPC分类号： H01L29/00 ,  H01L21/8228 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC分类号： H01L29/66818 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/785

摘要： One illustrative method disclosed herein includes, among other things, forming first and second fins for a short channel FinFET device (“SCD”) and a long channel FinFET device (“LCD”), performing an oxidation process to form a sacrificial oxide material selectively on the channel portion of one of the first and second fins but not on the channel portion of the other of the first and second fins, removing the sacrificial oxide material from the fin on which it is formed so as to produce a reduced-size channel portion on that fin that is less than the initial size of the channel portion of the other non-oxidized fin, and forming first and second gate structures for the SCD and LCD devices.

公开(公告)号：US10818557B2

公开(公告)日：2020-10-27

申请号：US16026130

申请日：2018-07-03

申请人： GLOBALFOUNDRIES INC.

发明人： Sipeng Gu ,  Akshey Sehgal ,  Xinyuan Dou ,  Sunil K. Singh ,  Ravi P. Srivastava ,  Haiting Wang ,  Scott H. Beasor

IPC分类号： H01L21/8234 ,  H01L29/423 ,  H01L23/48 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/49 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/66 ,  H01L29/08

摘要： This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor structure including two source/drain regions; a metal gate positioned on the semiconductor structure adjacent to and between the source/drain regions; a metal cap with a different metal composition than the metal gate and having a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm positioned on the metal gate; a first dielectric cap layer positioned above the semiconductor structure; an inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein an upper surface of the ILD has a greater height above the semiconductor structure than an upper surface of the metal gate; a second dielectric cap layer positioned on the ILD and above the metal cap; and a contact on and in electrical contact with the metal cap.