公开(公告)号：US11164794B2

公开(公告)日：2021-11-02

申请号：US16531114

申请日：2019-08-04

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Wei Hong ,  Liu Jiang ,  Yanping Shen

IPC: H01L29/76 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423

Abstract: A semiconductor device is provided that includes an active region above a substrate, a first gate structure, a second gate structure, a first semiconductor structure, a second semiconductor structure and a semiconductor bridge. The first gate semiconductor and the second semiconductor structure are in the active region and between the first and the second gate structures. The first semiconductor structure is adjacent to the first gate structure and a second semiconductor structure is adjacent to the second gate structure. The semiconductor bridge is in the active region electrically coupling the first and the second semiconductor structures.

公开(公告)号：US10957578B2

公开(公告)日：2021-03-23

申请号：US16146413

申请日：2018-09-28

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Wei Hong ,  Hui Zang ,  Hsien-Ching Lo ,  Zhenyu Hu ,  Liu Jiang

IPC: H01L21/762 ,  H01L27/12 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion break device and methods of manufacture. The structure includes a single diffusion break structure with a fill material between sidewall spacers of the single diffusion break structure and a channel oxidation below the fill material.

公开(公告)号：US11171036B2

公开(公告)日：2021-11-09

申请号：US16596814

申请日：2019-10-09

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yongjun Shi ,  Wei Hong ,  Chun Yu Wong ,  Halting Wang ,  Liu Jiang

IPC: H01L21/762 ,  H01L27/12

Abstract: A method and related structure provide a void-free dielectric over trench isolation region in an FDSOI substrate. The structure may include a first transistor including a first active gate over the substrate, a second transistor including a second active gate over the substrate, a first liner extending over the first transistor, and a second, different liner extending over the second transistor. A trench isolation region electrically isolates the first transistor from the second transistor. The trench isolation region includes a trench isolation extending into the FDSOI substrate and an inactive gate over the trench isolation. A dielectric extends over the inactive gate and in direct contact with an upper surface of the trench isolation region. The dielectric is void-free, and the liners do not extend over the trench isolation.

公开(公告)号：US20210249518A1

公开(公告)日：2021-08-12

申请号：US16788922

申请日：2020-02-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Wei Hong ,  Yanping Shen ,  Domingo A. Ferrer ,  Hong Yu

IPC: H01L29/45 ,  H01L29/417 ,  H01L29/08 ,  H01L27/088 ,  H01L29/165 ,  H01L21/285 ,  H01L29/66

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with a niobium-based silicide layer. An IC structure according to the disclosure includes a transistor on a substrate, the transistor including a gate structure above the substrate and a source/drain (S/D) region on the substrate adjacent the gate structure. A niobium-based silicide layer is on at least an upper surface the S/D region of the transistor, and extends across substantially an entire width of the S/D region. An S/D contact to the S/D region is in contact with the niobium-based silicide layer.

公开(公告)号：US20210111065A1

公开(公告)日：2021-04-15

申请号：US16596814

申请日：2019-10-09

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yongjun Shi ,  Wei Hong ,  Chun Yu Wong ,  Haiting Wang ,  Liu Jiang

IPC: H01L21/762 ,  H01L27/12

Abstract: A method and related structure provide a void-free dielectric over trench isolation region in an FDSOI substrate. The structure may include a first transistor including a first active gate over the substrate, a second transistor including a second active gate over the substrate, a first liner extending over the first transistor, and a second, different liner extending over the second transistor. A trench isolation region electrically isolates the first transistor from the second transistor. The trench isolation region includes a trench isolation extending into the FDSOI substrate and an inactive gate over the trench isolation. A dielectric extends over the inactive gate and in direct contact with an upper surface of the trench isolation region. The dielectric is void-free, and the liners do not extend over the trench isolation.

公开(公告)号：US11315835B2

公开(公告)日：2022-04-26

申请号：US16296469

申请日：2019-03-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Wei Hong ,  Hong Yu ,  Tao Chu ,  Bingwu Liu

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/308

Abstract: One illustrative method disclosed herein includes forming a conformal SMCM layer above a conformal high-k gate insulation layer within each of first and second replacement gate cavities (RGC), removing the SMCM layer from the first RGC while leaving the SMCM layer in position within the second RGC, forming a first conformal metal-containing material (MCM) layer above the gate insulation layer within the first RGC and above the SMCM layer in position within the second RGC, removing the first conformal MCM layer and the conformal SMCM layer positioned within the second RGC while leaving the first conformal MCM layer within the first RGC, and forming a second conformal MCM layer above the first conformal MCM layer positioned within the first RGC and above the gate insulation layer positioned within the second RGC.

公开(公告)号：US11239336B2

公开(公告)日：2022-02-01

申请号：US16788922

申请日：2020-02-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Wei Hong ,  Yanping Shen ,  Domingo A. Ferrer ,  Hong Yu

IPC: H01L29/45 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L27/088 ,  H01L29/165 ,  H01L29/78 ,  H01L21/285

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with a niobium-based silicide layer. An IC structure according to the disclosure includes a transistor on a substrate, the transistor including a gate structure above the substrate and a source/drain (S/D) region on the substrate adjacent the gate structure. A niobium-based silicide layer is on at least an upper surface the S/D region of the transistor, and extends across substantially an entire width of the S/D region. An S/D contact to the S/D region is in contact with the niobium-based silicide layer.

公开(公告)号：US11004953B2

公开(公告)日：2021-05-11

申请号：US16454016

申请日：2019-06-26

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Rinus Tek Po Lee ,  Hui Zang ,  Jiehui Shu ,  Hong Yu ,  Wei Hong

IPC: H01L29/66 ,  H01L21/8234

Abstract: A method is provided for fabricating a semiconductor device structure with a short channel and long channel component having different gate dielectric layers without using lithography processes or masks. The method includes forming first and second openings having sidewalls and bottom surfaces in a dielectric layer, the first opening being narrower than the second opening. A first material layer is formed in the first and second openings. A protective layer is formed over the first material layer, wherein the protective layer covers the sidewalls and the bottom surface of the second opening. A block layer is formed to fill the second opening and cover the protective layer therein. The method further includes removing side portions of the protective layer to expose upper portions of the first material layer in the second opening. The block layer is removed from the second opening to expose the protective layer remaining in the second opening. A second material layer is formed over the first material layer on the exposed upper portions of the first material layer in the second opening. An intermix layer is formed in the second opening using the first and second material layers. The protective layer from the second opening is removed to expose the first material layer.