公开(公告)号：US20240088157A1

公开(公告)日：2024-03-14

申请号：US17942233

申请日：2022-09-12

Applicant: GlobalFoundries U.S. Inc.

Inventor： Michel Abou-Khalil ,  Steven M. Shank ,  Sarah McTaggart ,  Aaron Vallett ,  Rajendran Krishnasamy ,  Megan Lydon-Nuhfer

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/76286 ,  H01L21/84

Abstract: Semiconductor device structures with device isolation and methods of forming a semiconductor device structure with device isolation. The structure comprises a semiconductor substrate, a first semiconductor layer on the semiconductor substrate, a second semiconductor layer in a cavity in the first semiconductor layer, and a device structure including a doped region in the second semiconductor layer. The first semiconductor layer comprises a porous semiconductor material, and the second semiconductor layer comprises a single-crystal semiconductor material.

公开(公告)号：US20230317776A1

公开(公告)日：2023-10-05

申请号：US17708561

申请日：2022-03-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Michel Abou-Khalil ,  Steven M. Shank ,  Aaron Vallett ,  Sarah McTaggart ,  Rajendran Krishnasamy

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/0649 ,  H01L29/4236 ,  H01L29/1087

Abstract: Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. The structure includes a semiconductor substrate having a first surface, a recess in the first surface, and a second surface inside the first recess. The structure further includes a shallow trench isolation region extending from the first surface into the semiconductor substrate. The shallow trench isolation region is positioned to surround an active device region including the recess. A field-effect transistor includes a gate electrode positioned on a portion of the second surface.

公开(公告)号：US12230673B2

公开(公告)日：2025-02-18

申请号：US17708561

申请日：2022-03-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Michel Abou-Khalil ,  Steven M. Shank ,  Aaron Vallett ,  Sarah McTaggart ,  Rajendran Krishnasamy

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/423

Abstract: Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. The structure includes a semiconductor substrate having a first surface, a recess in the first surface, and a second surface inside the first recess. The structure further includes a shallow trench isolation region extending from the first surface into the semiconductor substrate. The shallow trench isolation region is positioned to surround an active device region including the recess. A field-effect transistor includes a gate electrode positioned on a portion of the second surface.

公开(公告)号：US11658177B2

公开(公告)日：2023-05-23

申请号：US17113473

申请日：2020-12-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Michel J. Abou-Khalil ,  John J. Ellis-Monaghan ,  Randy Wolf ,  Alvin J. Joseph ,  Aaron Vallett

IPC: H01L27/02 ,  H01L29/06

CPC classification number: H01L27/0285 ,  H01L27/0218 ,  H01L29/0619 ,  H01L29/0649

Abstract: Semiconductor device structures with substrate biasing, methods of forming a semiconductor device structure with substrate biasing, and methods of operating a semiconductor device structure with substrate biasing. A substrate contact is coupled to a portion of a bulk semiconductor substrate in a device region. The substrate contact is configured to be biased with a negative bias voltage. A field-effect transistor includes a semiconductor body in the device region of the bulk semiconductor substrate. The semiconductor body is electrically isolated from the portion of the bulk semiconductor substrate.

公开(公告)号：US20220181317A1

公开(公告)日：2022-06-09

申请号：US17113473

申请日：2020-12-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Michel J. Abou-Khalil ,  John J. Ellis-Monaghan ,  Randy Wolf ,  Alvin J. Joseph ,  Aaron Vallett

IPC: H01L27/02 ,  H01L29/06

Abstract: Semiconductor device structures with substrate biasing, methods of forming a semiconductor device structure with substrate biasing, and methods of operating a semiconductor device structure with substrate biasing. A substrate contact is coupled to a portion of a bulk semiconductor substrate in a device region. The substrate contact is configured to be biased with a negative bias voltage. A field-effect transistor includes a semiconductor body in the device region of the bulk semiconductor substrate. The semiconductor body is electrically isolated from the portion of the bulk semiconductor substrate.

公开(公告)号：US11315825B2

公开(公告)日：2022-04-26

申请号：US16553737

申请日：2019-08-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michel J. Abou-Khalil ,  Aaron Vallett ,  Steven M. Shank ,  Bojidha Babu ,  John J. Ellis-Monaghan ,  Anthony K. Stamper

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/265 ,  H01L21/324

Abstract: Structures including electrical isolation and methods associated with forming such structures. A semiconductor layer has a top surface, a polycrystalline region, and a single-crystal region between the polycrystalline region and the top surface. An isolation band is located beneath the single-crystal region. The isolation band contains a first concentration of an n-type dopant and a second concentration of a p-type dopant, and a net difference between the first concentration and the second concentration is within a range of about five percent to about fifteen percent.