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    Systems and methods of pipelined output latching involving synchronous memory arrays
    3.
    发明授权
    Systems and methods of pipelined output latching involving synchronous memory arrays 有权
    包括同步存储器阵列的流水线输出锁存的系统和方法

    公开(公告)号：US09053768B2

    公开(公告)日：2015-06-09

    申请号：US14203416

    申请日：2014-03-10

    申请人： GSI TECHNOLOGY, INC.

    发明人： Lee-Lean Shu ,  Yoshinori Sato

    IPC分类号： G11C7/22 ,  G11C11/4076 ,  G11C7/06 ,  G11C7/08 ,  G11C7/10 ,  G11C11/4096

    CPC分类号： G11C7/1039 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/419 ,  G11C29/028 ,  G11C2207/2272

    摘要： Systems and methods of synchronous memories and synchronous memory operation are disclosed. According to one illustrative implementation, a memory device is disclosed comprising memory circuitry having a memory output, the memory circuitry including a sense amplifier having a first output and a second output, a first data path coupled to the first output of the sense amplifier, the first data path including 2 latches/registers, and a second data path coupled to the second output of the sense amplifier, the second data path including a plurality latches/registers. In further implementations, various control circuitry, connections and control signals may be utilized to operate the latches/registers in the first and second data paths according to specified configurations, control, modes, latency and/or timing domain information, to achieve, for example, pipelined output latching and/or double data rate output.

    摘要翻译： 公开了同步存储器和同步存储器操作的系统和方法。 根据一个说明性实现，公开了一种存储器件，其包括具有存储器输出的存储器电路，所述存储器电路包括具有第一输出和第二输出的读出放大器，耦合到读出放大器的第一输出的第一数据通路， 包括2个锁存器/寄存器的第一数据路径和耦合到读出放大器的第二输出的第二数据路径，第二数据路径包括多个锁存器/寄存器。 在进一步的实现中，可以使用各种控制电路，连接和控制信号来根据指定的配置，控制，模式，等待时间和/或定时域信息来操作第一和第二数据路径中的锁存器/寄存器，以实现例如 ，流水线输出锁存和/或双倍数据速率输出。

    Systems and methods of pipelined output latching involving synchronous memory arrays
    5.
    发明授权
    Systems and methods of pipelined output latching involving synchronous memory arrays 有权

    公开(公告)号：US10535381B2

    公开(公告)日：2020-01-14

    申请号：US15933291

    申请日：2018-03-22

    申请人： GSI Technology, Inc.

    发明人： Lee-Lean Shu ,  Yoshinori Sato

    IPC分类号： G11C7/10 ,  G11C7/06 ,  G11C11/419 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C8/18 ,  G11C29/02

    摘要： Systems and methods of synchronous memories and synchronous memory operation are disclosed. According to one illustrative implementation, a memory device is disclosed comprising memory circuitry having a memory output, the memory circuitry including a sense amplifier having a first output and a second output, a first data path coupled to the first output of the sense amplifier, the first data path including 2 latches/registers, and a second data path coupled to the second output of the sense amplifier, the second data path including a plurality latches/registers. In further implementations, various control circuitry, connections and control signals may be utilized to operate the latches/registers in the first and second data paths according to specified configurations, control, modes, latency and/or timing domain information, to achieve, for example, pipelined output latching and/or double data rate output.

    Systems and methods involving phase detection with adaptive locking/detection features
    7.
    发明授权
    Systems and methods involving phase detection with adaptive locking/detection features 有权
    涉及具有自适应锁定/检测特征的相位检测的系统和方法

    公开(公告)号：US09018992B1

    公开(公告)日：2015-04-28

    申请号：US14161623

    申请日：2014-01-22

    申请人： GSI Technology, Inc.

    发明人： Jyn-Bang Shyu ,  Yoshinori Sato ,  Jae Hyeong Kim ,  Lee-Lean Shu

    IPC分类号： H03L7/06 ,  H03L7/095

    CPC分类号： H03L7/095 ,  H03L7/0814 ,  H03L7/0816

    摘要： Systems and methods associated with control of clock signals are disclosed. In one exemplary implementation, there is provided a delay-lock-loop (DLL) and/or a delay/phase detection circuit. Moreover, such circuit may comprise digital phase detection circuitry, digital delay control circuitry, analog phase detection circuitry, and analog delay control circuitry. Implementations may include configurations that prevent transition back to the unlocked state due to jitter or noise.

    摘要翻译： 公开了与控制时钟信号相关联的系统和方法。 在一个示例性实现中，提供了延迟锁定环（DLL）和/或延迟/相位检测电路。 此外，这种电路可以包括数字相位检测电路，数字延迟控制电路，模拟相位检测电路和模拟延迟控制电路。 实现可以包括由于抖动或噪声而防止转换回解锁状态的配置。