公开(公告)号：US20080042173A1

公开(公告)日：2008-02-21

申请号：US11839387

申请日：2007-08-15

Applicant: Gab-Jin NAM ,  Myoung-Bum LEE

Inventor： Gab-Jin NAM ,  Myoung-Bum LEE

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/28088 ,  H01L29/4966 ,  H01L29/78

Abstract: A MOS transistor includes a substrate, source/drain regions formed at portions of the substrate, and a channel region formed between the source/drain regions. The MOS transistor further includes a gate structure having a gate insulation layer pattern and a gate electrode formed on the channel region. The gate electrode includes a first gate conductive layer pattern and a second gate conductive layer pattern. The first gate conductive layer pattern has a nitrogen concentration gradient gradually increasing from a lower portion of the first gate conductive layer pattern to an upper portion of the first gate conductive layer pattern. The second gate conductive layer pattern includes a material having a resistance substantially lower than a resistance of the first gate conductive layer pattern.

Abstract translation: MOS晶体管包括衬底，形成在衬底的部分处的源极/漏极区域和形成在源极/漏极区域之间的沟道区域。 MOS晶体管还包括具有栅极绝缘层图案的栅极结构和形成在沟道区上的栅电极。 栅电极包括第一栅极导电层图案和第二栅极导电层图案。 第一栅极导电层图案具有从第一栅极导电层图案的下部逐渐增加到第一栅极导电层图案的上部的氮浓度梯度。 第二栅极导电层图案包括具有基本上低于第一栅极导电层图案的电阻的电阻的材料。

公开(公告)号：US20150041913A1

公开(公告)日：2015-02-12

申请号：US14192074

申请日：2014-02-27

Applicant: Tae-Hyun AN ,  Toshiro NAKANISHI ,  Gab-Jin NAM ,  Jong-Ho LEE

Inventor： Tae-Hyun AN ,  Toshiro NAKANISHI ,  Gab-Jin NAM ,  Jong-Ho LEE

IPC: H01L29/78 ,  H01L27/092

CPC classification number: H01L29/7856 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

Abstract: A semiconductor device includes a substrate including an NMOS region, a fin active region protruding from the substrate in the NMOS region, the fin active region including an upper surface and a sidewall, a gate dielectric layer on the upper surface and the sidewall of the fin active region, a first metal gate electrode on the gate dielectric layer, the first metal gate electrode having a first thickness at the upper surface of the fin active region and a second thickness at the sidewall of the fin active region, and a second metal gate electrode on the first metal gate electrode, the second metal gate electrode having a third thickness at the upper surface of the fin active region and a fourth thickness at the sidewall of the fin active region, wherein the third thickness is less than the fourth thickness.

Abstract translation: 半导体器件包括：衬底，其包括NMOS区，在NMOS区中从衬底突出的鳍有源区，鳍有源区包括上表面和侧壁;栅极电介质层，位于鳍的上表面和侧壁上 有源区，栅极电介质层上的第一金属栅电极，第一金属栅电极在翅片有源区的上表面具有第一厚度，在鳍有源区的侧壁具有第二厚度，第二金属栅电极 所述第二金属栅电极在所述翅片有源区的上表面具有第三厚度，在所述鳍有源区的所述侧壁处具有第四厚度，其中所述第三厚度小于所述第四厚度。

公开(公告)号：US20140291755A1

公开(公告)日：2014-10-02

申请号：US14167053

申请日：2014-01-29

Applicant: Sung-Kweon BAEK ,  Gab-Jin NAM ,  Jin-Soak KIM ,  Ji-Young MIN ,  Eun-Ae CHUNG

Inventor： Sung-Kweon BAEK ,  Gab-Jin NAM ,  Jin-Soak KIM ,  Ji-Young MIN ,  Eun-Ae CHUNG

IPC: H01L29/423 ,  H01L27/108 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L29/7827

Abstract: A semiconductor device includes a first source/drain region and a second source/drain region disposed in an active region of a semiconductor substrate, and a gate structure crossing the active region and disposed between the first and second source/drain regions, the gate structure including a gate electrode having a first part and a second part on the first part, the gate electrode being at a lower level than an upper surface of the active region, an insulating capping pattern on the gate electrode, a gate dielectric between the gate electrode and the active region, and an empty space between the active region and the second part of the gate electrode.

Abstract translation: 半导体器件包括设置在半导体衬底的有源区中的第一源极/漏极区域和第二源极/漏极区域以及与有源区域交叉并设置在第一和第二源极/漏极区域之间的栅极结构，栅极结构 包括在第一部分具有第一部分和第二部分的栅电极，栅电极处于比有源区的上表面更低的电平，栅电极上的绝缘封盖图案，栅电极之间的栅极电介质 和有源区，以及有源区和栅电极的第二部分之间的空白空间。