公开(公告)号：US20080042173A1

公开(公告)日：2008-02-21

申请号：US11839387

申请日：2007-08-15

Applicant: Gab-Jin NAM ,  Myoung-Bum LEE

Inventor： Gab-Jin NAM ,  Myoung-Bum LEE

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/28088 ,  H01L29/4966 ,  H01L29/78

Abstract: A MOS transistor includes a substrate, source/drain regions formed at portions of the substrate, and a channel region formed between the source/drain regions. The MOS transistor further includes a gate structure having a gate insulation layer pattern and a gate electrode formed on the channel region. The gate electrode includes a first gate conductive layer pattern and a second gate conductive layer pattern. The first gate conductive layer pattern has a nitrogen concentration gradient gradually increasing from a lower portion of the first gate conductive layer pattern to an upper portion of the first gate conductive layer pattern. The second gate conductive layer pattern includes a material having a resistance substantially lower than a resistance of the first gate conductive layer pattern.

Abstract translation: MOS晶体管包括衬底，形成在衬底的部分处的源极/漏极区域和形成在源极/漏极区域之间的沟道区域。 MOS晶体管还包括具有栅极绝缘层图案的栅极结构和形成在沟道区上的栅电极。 栅电极包括第一栅极导电层图案和第二栅极导电层图案。 第一栅极导电层图案具有从第一栅极导电层图案的下部逐渐增加到第一栅极导电层图案的上部的氮浓度梯度。 第二栅极导电层图案包括具有基本上低于第一栅极导电层图案的电阻的电阻的材料。

公开(公告)号：US20120007165A1

公开(公告)日：2012-01-12

申请号：US13181281

申请日：2011-07-12

Applicant: Myoung-Bum LEE ,  Jae-Hwang SIM ,  In-Sun PARK ,  Jin-Gi HONG ,  Ju-Seon GOO ,  Seung-Bae PARK ,  Seung-Yup LEE ,  Du-Heon SONG ,  Jeong-Dong CHOE ,  Seok-Won LEE

Inventor： Myoung-Bum LEE ,  Jae-Hwang SIM ,  In-Sun PARK ,  Jin-Gi HONG ,  Ju-Seon GOO ,  Seung-Bae PARK ,  Seung-Yup LEE ,  Du-Heon SONG ,  Jeong-Dong CHOE ,  Seok-Won LEE

IPC: H01L29/788 ,  H01L27/088

CPC classification number: H01L29/7881 ,  H01L21/764 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor device includes a substrate, a plurality of gate structures, a first insulating interlayer pattern, and a second insulation layer pattern. The substrate has an active region and a field region, each of the active region and the field region extends in a first direction, and the active region and the field region are alternately and repeatedly arranged in a second direction substantially perpendicular to the first direction. The gate structures are spaced apart from each other in the first direction, each of the gate structures extends in the second direction. The first insulation layer pattern is formed on a portion of a sidewall of each gate structure. The second insulation layer pattern covers the gate structures and the first insulation layer pattern, and has an air tunnel between the gate structures, the air tunnel extending in the second direction.

Abstract translation: 半导体器件包括衬底，多个栅极结构，第一绝缘层间图案和第二绝缘层图案。 基板具有有源区域和场区域，有源区域和场区域中的每一个沿着第一方向延伸，并且有源区域和场区域在基本上垂直于第一方向的第二方向上交替地和重复地布置。 栅极结构在第一方向上彼此间隔开，每个栅极结构沿第二方向延伸。 第一绝缘层图案形成在每个栅极结构的侧壁的一部分上。 第二绝缘层图案覆盖栅极结构和第一绝缘层图案，并且在栅极结构之间具有沿第二方向延伸的空气通道的空气通道。

公开(公告)号：US20080032512A1

公开(公告)日：2008-02-07

申请号：US11828541

申请日：2007-07-26

Applicant: Dong-Chan KIM ,  Seong-Hoon JEONG ,  Myoung-Bum LEE ,  Sang-Bom KANG ,  Jin-Hwa HEO

Inventor： Dong-Chan KIM ,  Seong-Hoon JEONG ,  Myoung-Bum LEE ,  Sang-Bom KANG ,  Jin-Hwa HEO

IPC: H01L21/31

CPC classification number: H01L21/0214 ,  H01L21/02252 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/518 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor device in a process camber is disclosed. The method includes forming a preliminary dielectric layer including oxynitride on a substrate by performing a plasma oxidation treatment and a first plasma nitridation treatment, wherein the preliminary dielectric layer has a substantially uniform nitrogen concentration profile to a defined depth, and forming a dielectric layer from the preliminary dielectric layer by performing a second plasma nitridation treatment, wherein the nitrogen concentration of the dielectric layer is higher than that of the preliminary dielectric layer.

Abstract translation: 公开了一种制造半导体器件的方法。 该方法包括通过进行等离子体氧化处理和第一等离子体氮化处理在衬底上形成包括氧氮化物的预备电介质层，其中预备电介质层具有基本上均匀的氮浓度分布到规定的深度，并且从 通过进行第二等离子体氮化处理，其中所述电介质层的氮浓度高于所述预备介电层的氮浓度。