公开(公告)号：US09153696B2

公开(公告)日：2015-10-06

申请号：US14192074

申请日：2014-02-27

申请人： Tae-Hyun An ,  Toshiro Nakanishi ,  Gab-Jin Nam ,  Jong-Ho Lee

发明人： Tae-Hyun An ,  Toshiro Nakanishi ,  Gab-Jin Nam ,  Jong-Ho Lee

IPC分类号： H01L29/78 ,  H01L27/092 ,  H01L21/8238

CPC分类号： H01L29/7856 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

摘要： A semiconductor device includes a substrate including an NMOS region, a fin active region protruding from the substrate in the NMOS region, the fin active region including an upper surface and a sidewall, a gate dielectric layer on the upper surface and the sidewall of the fin active region, a first metal gate electrode on the gate dielectric layer, the first metal gate electrode having a first thickness at the upper surface of the fin active region and a second thickness at the sidewall of the fin active region, and a second metal gate electrode on the first metal gate electrode, the second metal gate electrode having a third thickness at the upper surface of the fin active region and a fourth thickness at the sidewall of the fin active region, wherein the third thickness is less than the fourth thickness.

摘要翻译： 半导体器件包括：衬底，其包括NMOS区，在NMOS区中从衬底突出的鳍有源区，鳍有源区包括上表面和侧壁;栅极电介质层，位于鳍的上表面和侧壁上 有源区，栅极电介质层上的第一金属栅电极，第一金属栅电极在翅片有源区的上表面具有第一厚度，在鳍有源区的侧壁具有第二厚度，第二金属栅电极 所述第二金属栅电极在所述翅片有源区的上表面具有第三厚度，在所述鳍有源区的所述侧壁处具有第四厚度，其中所述第三厚度小于所述第四厚度。

公开(公告)号：US20150041913A1

公开(公告)日：2015-02-12

申请号：US14192074

申请日：2014-02-27

申请人： Tae-Hyun AN ,  Toshiro NAKANISHI ,  Gab-Jin NAM ,  Jong-Ho LEE

发明人： Tae-Hyun AN ,  Toshiro NAKANISHI ,  Gab-Jin NAM ,  Jong-Ho LEE

IPC分类号： H01L29/78 ,  H01L27/092

CPC分类号： H01L29/7856 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

摘要： A semiconductor device includes a substrate including an NMOS region, a fin active region protruding from the substrate in the NMOS region, the fin active region including an upper surface and a sidewall, a gate dielectric layer on the upper surface and the sidewall of the fin active region, a first metal gate electrode on the gate dielectric layer, the first metal gate electrode having a first thickness at the upper surface of the fin active region and a second thickness at the sidewall of the fin active region, and a second metal gate electrode on the first metal gate electrode, the second metal gate electrode having a third thickness at the upper surface of the fin active region and a fourth thickness at the sidewall of the fin active region, wherein the third thickness is less than the fourth thickness.

摘要翻译： 半导体器件包括：衬底，其包括NMOS区，在NMOS区中从衬底突出的鳍有源区，鳍有源区包括上表面和侧壁;栅极电介质层，位于鳍的上表面和侧壁上 有源区，栅极电介质层上的第一金属栅电极，第一金属栅电极在翅片有源区的上表面具有第一厚度，在鳍有源区的侧壁具有第二厚度，第二金属栅电极 所述第二金属栅电极在所述翅片有源区的上表面具有第三厚度，在所述鳍有源区的所述侧壁处具有第四厚度，其中所述第三厚度小于所述第四厚度。

公开(公告)号：US20080179648A1

公开(公告)日：2008-07-31

申请号：US12000504

申请日：2007-12-13

申请人： Dae-won Ha ,  Tae-hyun An ,  Min-young Shim

发明人： Dae-won Ha ,  Tae-hyun An ,  Min-young Shim

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L29/94 ,  H01L21/823418 ,  H01L27/0629 ,  H01L27/105

摘要： A semiconductor device having a semiconductor substrate including a first region and a second region is provided. The semiconductor device further includes a gate electrode on the first region and having a first sidewall and a second sidewall, a first source region in the first region proximate to the first sidewall, a first drain region in the first region proximate to the second sidewall, an upper electrode on the second region and having a first sidewall and a second sidewall, a second source region in the second region proximate to the first sidewall of the upper electrode, and a second drain region in the second region proximate to the second sidewall of the upper electrode, wherein an impurity doping concentration of the first source region and the first drain region is greater than an impurity doping concentration of the second source region and the second drain region.

摘要翻译： 提供具有包括第一区域和第二区域的半导体衬底的半导体器件。 所述半导体器件还包括位于所述第一区域上并具有第一侧壁和第二侧壁的栅电极，所述第一区域中靠近所述第一侧壁的第一源极区域，所述第一区域中靠近所述第二侧壁的第一漏极区域， 在第二区域上的上电极，具有第一侧壁和第二侧壁，第二区域中靠近上电极的第一侧壁的第二区域，以及靠近第二侧壁的第二区域中的第二漏极区域 所述上电极，其中所述第一源极区域和所述第一漏极区域的杂质掺杂浓度大于所述第二源极区域和所述第二漏极区域的杂质掺杂浓度。

公开(公告)号：US07402478B2

公开(公告)日：2008-07-22

申请号：US11465420

申请日：2006-08-17

申请人： Tae-Hyun An

发明人： Tae-Hyun An

IPC分类号： H01L21/8238

CPC分类号： H01L29/66545 ,  H01L21/28061 ,  H01L21/32155 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/4236 ,  H01L29/4933 ,  H01L29/66621

摘要： In an embodiment, a method of fabricating a dual gate electrode includes forming an initial semiconductor layer doped with impurities of a first conductivity type on a semiconductor substrate having a first region and a second region. The initial semiconductor layer of the second region is partially etched to form a recessed semiconductor layer that is thinner than the initial semiconductor layer. Impurities of a second conductivity type different from the first conductivity type are implanted into the recessed semiconductor layer to define a first semiconductor layer in the first region and a second semiconductor layer in the second region, respectively. Then, the first and second semiconductor layers are annealed, and the annealed first semiconductor layer is planarized. The resulting structure may be etched to form gate electrodes that are capable of having high concentrations of impurities.

摘要翻译： 在一个实施例中，制造双栅电极的方法包括在具有第一区域和第二区域的半导体衬底上形成掺杂有第一导电类型的杂质的初始半导体层。 部分地蚀刻第二区域的初始半导体层以形成比初始半导体层薄的凹陷半导体层。 不同于第一导电类型的第二导电类型的杂质被注入到凹陷半导体层中以在第一区域中分别限定第一半导体层和在第二区域中限定第二半导体层。 然后，对第一和第二半导体层进行退火，将退火的第一半导体层平坦化。 所得到的结构可以被蚀刻以形成能够具有高浓度杂质的栅电极。

公开(公告)号：US20070048914A1

公开(公告)日：2007-03-01

申请号：US11465420

申请日：2006-08-17

申请人： Tae-Hyun AN

发明人： Tae-Hyun AN

IPC分类号： H01L21/84

CPC分类号： H01L29/66545 ,  H01L21/28061 ,  H01L21/32155 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/4236 ,  H01L29/4933 ,  H01L29/66621

摘要： In an embodiment, a method of fabricating a dual gate electrode includes forming an initial semiconductor layer doped with impurities of a first conductivity type on a semiconductor substrate having a first region and a second region. The initial semiconductor layer of the second region is partially etched to form a recessed semiconductor layer that is thinner than the initial semiconductor layer. Impurities of a second conductivity type different from the first conductivity type are implanted into the recessed semiconductor layer to define a first semiconductor layer in the first region and a second semiconductor layer in the second region, respectively. Then, the first and second semiconductor layers are annealed, and the annealed first semiconductor layer is planarized. The resulting structure may be etched to form gate electrodes that are capable of having high concentrations of impurities.

摘要翻译： 在一个实施例中，制造双栅电极的方法包括在具有第一区域和第二区域的半导体衬底上形成掺杂有第一导电类型的杂质的初始半导体层。 部分地蚀刻第二区域的初始半导体层以形成比初始半导体层薄的凹陷半导体层。 不同于第一导电类型的第二导电类型的杂质被注入到凹陷半导体层中以在第一区域中分别限定第一半导体层和在第二区域中限定第二半导体层。 然后，对第一和第二半导体层进行退火，将退火的第一半导体层平坦化。 所得到的结构可以被蚀刻以形成能够具有高浓度杂质的栅电极。

公开(公告)号：US08004023B2

公开(公告)日：2011-08-23

申请号：US12000504

申请日：2007-12-13

申请人： Dae-won Ha ,  Tae-hyun An ,  Min-young Shim

发明人： Dae-won Ha ,  Tae-hyun An ,  Min-young Shim

IPC分类号： H01L29/76

CPC分类号： H01L29/94 ,  H01L21/823418 ,  H01L27/0629 ,  H01L27/105

摘要： A semiconductor device having a semiconductor substrate including a first region and a second region is provided. The semiconductor device further includes a gate electrode on the first region and having a first sidewall and a second sidewall, a first source region in the first region proximate to the first sidewall, a first drain region in the first region proximate to the second sidewall, an upper electrode on the second region and having a first sidewall and a second sidewall, a second source region in the second region proximate to the first sidewall of the upper electrode, and a second drain region in the second region proximate to the second sidewall of the upper electrode, wherein an impurity doping concentration of the first source region and the first drain region is greater than an impurity doping concentration of the second source region and the second drain region.

摘要翻译： 提供具有包括第一区域和第二区域的半导体衬底的半导体器件。 所述半导体器件还包括位于所述第一区域上并具有第一侧壁和第二侧壁的栅电极，所述第一区域中靠近所述第一侧壁的第一源极区域，所述第一区域中靠近所述第二侧壁的第一漏极区域， 在第二区域上的上电极，具有第一侧壁和第二侧壁，第二区域中靠近上电极的第一侧壁的第二区域，以及靠近第二侧壁的第二区域中的第二漏极区域 所述上电极，其中所述第一源极区域和所述第一漏极区域的杂质掺杂浓度大于所述第二源极区域和所述第二漏极区域的杂质掺杂浓度。