公开(公告)号：US09153696B2

公开(公告)日：2015-10-06

申请号：US14192074

申请日：2014-02-27

申请人： Tae-Hyun An ,  Toshiro Nakanishi ,  Gab-Jin Nam ,  Jong-Ho Lee

发明人： Tae-Hyun An ,  Toshiro Nakanishi ,  Gab-Jin Nam ,  Jong-Ho Lee

IPC分类号： H01L29/78 ,  H01L27/092 ,  H01L21/8238

CPC分类号： H01L29/7856 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

摘要： A semiconductor device includes a substrate including an NMOS region, a fin active region protruding from the substrate in the NMOS region, the fin active region including an upper surface and a sidewall, a gate dielectric layer on the upper surface and the sidewall of the fin active region, a first metal gate electrode on the gate dielectric layer, the first metal gate electrode having a first thickness at the upper surface of the fin active region and a second thickness at the sidewall of the fin active region, and a second metal gate electrode on the first metal gate electrode, the second metal gate electrode having a third thickness at the upper surface of the fin active region and a fourth thickness at the sidewall of the fin active region, wherein the third thickness is less than the fourth thickness.

摘要翻译： 半导体器件包括：衬底，其包括NMOS区，在NMOS区中从衬底突出的鳍有源区，鳍有源区包括上表面和侧壁;栅极电介质层，位于鳍的上表面和侧壁上 有源区，栅极电介质层上的第一金属栅电极，第一金属栅电极在翅片有源区的上表面具有第一厚度，在鳍有源区的侧壁具有第二厚度，第二金属栅电极 所述第二金属栅电极在所述翅片有源区的上表面具有第三厚度，在所述鳍有源区的所述侧壁处具有第四厚度，其中所述第三厚度小于所述第四厚度。

公开(公告)号：US20140024189A1

公开(公告)日：2014-01-23

申请号：US13943911

申请日：2013-07-17

申请人： Bi-O Kim ,  Toshiro Nakanishi ,  Jin-Tae Noh ,  Chang-Woo Sun ,  Seung-Hyun Lim ,  Jae-Young Ahn ,  Ki-Hyun Hwang

发明人： Bi-O Kim ,  Toshiro Nakanishi ,  Jin-Tae Noh ,  Chang-Woo Sun ,  Seung-Hyun Lim ,  Jae-Young Ahn ,  Ki-Hyun Hwang

IPC分类号： H01L29/66

CPC分类号： H01L29/66666 ,  H01L21/8239 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： Methods of fabricating vertical memory devices are provided including forming a plurality of alternating insulating layers and sacrificial layers on a substrate; patterning and etching the plurality of insulating layer and sacrificial layers to define an opening that exposes at least a portion of a surface of the substrate; forming a charge trapping pattern and a tunnel insulating pattern on a side wall of the opening; forming a channel layer on the tunnel insulating layer on the sidewall of the opening, the channel layer including N-type impurity doped polysilicon; forming a buried insulating pattern on the channel layer in the opening; and forming a blocking dielectric layer and a control gate on the charge trapping pattern of one side wall of the channel layer.

摘要翻译： 提供制造垂直存储器件的方法包括在衬底上形成多个交替绝缘层和牺牲层; 图案化和蚀刻所述多个绝缘层和牺牲层以限定暴露所述衬底的表面的至少一部分的开口; 在开口的侧壁上形成电荷捕获图案和隧道绝缘图案; 在开口的侧壁上的隧道绝缘层上形成沟道层，沟道层包括N型杂质掺杂多晶硅; 在开口中的沟道层上形成掩埋绝缘图案; 以及在沟道层的一个侧壁的电荷捕获图案上形成阻挡电介质层和控制栅极。

公开(公告)号：US20130334593A1

公开(公告)日：2013-12-19

申请号：US13972533

申请日：2013-08-21

申请人： Kwang-Soo SEOL ,  Chanjin PARK ,  Ki-Hyun HWANG ,  Hanmei CHOI ,  Sunghoi HUR ,  Wansik HWANG ,  Toshiro NAKANISHI ,  Kwangmin PARK ,  Ju-Yul LEE

发明人： Kwang-Soo SEOL ,  Chanjin PARK ,  Ki-Hyun HWANG ,  Hanmei CHOI ,  Sunghoi HUR ,  Wansik HWANG ,  Toshiro NAKANISHI ,  Kwangmin PARK ,  Ju-Yul LEE

IPC分类号： H01L29/792

CPC分类号： H01L29/42348 ,  H01L21/32137 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/511 ,  H01L29/517 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

公开(公告)号：US08278698B2

公开(公告)日：2012-10-02

申请号：US12703066

申请日：2010-02-09

申请人： Toshiro Nakanishi ,  Chanjin Park ,  Siyoung Choi ,  Bonyoung Koo

发明人： Toshiro Nakanishi ,  Chanjin Park ,  Siyoung Choi ,  Bonyoung Koo

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/11565

摘要： A nonvolatile memory device includes a device isolation pattern, a charge trap layer, and a plurality of word lines. The device isolation pattern defines an active region in a semiconductor substrate and extends in a first direction. The charge trap layer covers the active region and the device isolation pattern. The word lines on the charge trap layer cross the active region and extend in a second direction. The charge trap layer disposed in a first region where the word line and the active region cross each other has a different nitrogen content ratio from the charge trap layer disposed in a second region surrounding the first region.

摘要翻译： 非易失性存储器件包括器件隔离图案，电荷陷阱层和多个字线。 器件隔离图案限定半导体衬底中的有源区并沿第一方向延伸。 电荷陷阱层覆盖有源区和器件隔离图案。 电荷陷阱层上的字线穿过有源区并沿第二方向延伸。 设置在字线和有源区彼此交叉的第一区域中的电荷陷阱层与设置在围绕第一区域的第二区域中的电荷陷阱层具有不同的氮含量比。

公开(公告)号：US5504022A

公开(公告)日：1996-04-02

申请号：US172279

申请日：1993-12-23

申请人： Toshiro Nakanishi ,  Yasuhisa Sato

发明人： Toshiro Nakanishi ,  Yasuhisa Sato

IPC分类号： H01L21/316 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11517 ,  Y10S148/138 ,  Y10S438/964

摘要： A method of forming a non-volatile semiconductor memory device includes the steps of forming a generally periodical undulation on a surface of a silicon substrate with a pitch of 1-20 nm, by cleaning the surface of the substrate by a cleaning solution to form a native silicon oxide film that covers the surface of the silicon substrate with a thickness that changes generally periodically, followed by a selective etching process applied to the native silicon oxide film thus formed to expose the surface of the silicon substrate, and forming a tunneling oxide film on the undulated surface of the substrate by applying a thermal oxidation such that the tunneling oxide film has a thickness that changes generally periodically with a pitch of 1-20 nm.

摘要翻译： 形成非易失性半导体存储器件的方法包括以下步骤：通过清洗溶液清洗衬底的表面，以1-20nm的间距在硅衬底的表面上形成大致周期性的起伏，以形成 天然氧化硅膜，其覆盖硅衬底的表面，其厚度通常周期性地变化，随后是对由此形成的天然氧化硅膜施加的选择性蚀刻工艺以暴露硅衬底的表面，并且形成隧道氧化膜 通过施加热氧化使得隧道氧化物膜具有以1-20nm的间距大致周期性地变化的厚度，在衬底的起伏表面上。

公开(公告)号：US08123505B2

公开(公告)日：2012-02-28

申请号：US11728402

申请日：2007-03-26

申请人： Toshiro Nakanishi

发明人： Toshiro Nakanishi

IPC分类号： F16J15/00

CPC分类号： F04B53/164 ,  Y10S277/908 ,  Y10S277/909

摘要： An objective is to provide a reciprocating pump kept from lowering its performances, while restraining the cost from increasing.Collars 14, 20, 21 made of a material more excellent in resistance to corrosion than a manifold 3 are interposed between the manifold 3 and sealing members 10, 22, 23 for liquid-tightly sealing the manifold 3, so as to prevent the parts in contact with the sealing members 10, 22, 23 from being corroded by a liquid for use, and fully exhibit sealing functions, thereby preventing leakage from occurring in a pump chamber 4 and the pressure oscillation from being increased by the leakage, while the collars 14, 20, 21 made of the material excellent in resistance to leakage are used only in the parts in contact with the sealing members 10, 22, 23.

摘要翻译： 目的是提供一种不会降低其性能的往复泵，同时限制成本增加。 在歧管3与用于液密地密封歧管3的密封构件10,22,23之间插入由比歧管3更耐腐蚀的材料制成的环14,20,21，以防止部件 与密封构件10,22,23的接触不被被使用的液体腐蚀，并且充分地表现出密封功能，从而防止在泵室4中发生泄漏并且压力振荡不会因泄漏而增加，同时套环14 ，20,21由耐泄漏性优异的材料制成，仅与密封部件10,22,23接触的部分使用。

公开(公告)号：US20100252909A1

公开(公告)日：2010-10-07

申请号：US12754913

申请日：2010-04-06

申请人： Toshiro Nakanishi ,  Jeonghee Han ,  Soodoo Chae

发明人： Toshiro Nakanishi ,  Jeonghee Han ,  Soodoo Chae

IPC分类号： H01L27/06 ,  H01L29/92 ,  H01L29/8605

CPC分类号： H01L27/1021 ,  G11C13/0004 ,  G11C2213/71 ,  H01L27/101

摘要： An integrated circuit memory device may include a semiconductor substrate and a plurality of word-line layers wherein adjacent word-line layers are separated by respective word-line insulating layers. A plurality of active pillars may extend from a surface of the semiconductor substrate through the plurality of word-line layers and insulating layers. Dielectric information storage layers may be provided between the active pillars and the respective word-line layers. Related methods of operation and fabrication are also discussed.

摘要翻译： 集成电路存储器件可以包括半导体衬底和多个字线层，其中相邻的字线层由相应的字线绝缘层分开。 多个活性柱可以从半导体衬底的表面延伸穿过多个字线层和绝缘层。 电介质信息存储层可以设置在活动柱和相应的字线层之间。 还讨论了相关的操作和制造方法。

公开(公告)号：US20150041913A1

公开(公告)日：2015-02-12

申请号：US14192074

申请日：2014-02-27

申请人： Tae-Hyun AN ,  Toshiro NAKANISHI ,  Gab-Jin NAM ,  Jong-Ho LEE

发明人： Tae-Hyun AN ,  Toshiro NAKANISHI ,  Gab-Jin NAM ,  Jong-Ho LEE

IPC分类号： H01L29/78 ,  H01L27/092

CPC分类号： H01L29/7856 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

摘要： A semiconductor device includes a substrate including an NMOS region, a fin active region protruding from the substrate in the NMOS region, the fin active region including an upper surface and a sidewall, a gate dielectric layer on the upper surface and the sidewall of the fin active region, a first metal gate electrode on the gate dielectric layer, the first metal gate electrode having a first thickness at the upper surface of the fin active region and a second thickness at the sidewall of the fin active region, and a second metal gate electrode on the first metal gate electrode, the second metal gate electrode having a third thickness at the upper surface of the fin active region and a fourth thickness at the sidewall of the fin active region, wherein the third thickness is less than the fourth thickness.

摘要翻译： 半导体器件包括：衬底，其包括NMOS区，在NMOS区中从衬底突出的鳍有源区，鳍有源区包括上表面和侧壁;栅极电介质层，位于鳍的上表面和侧壁上 有源区，栅极电介质层上的第一金属栅电极，第一金属栅电极在翅片有源区的上表面具有第一厚度，在鳍有源区的侧壁具有第二厚度，第二金属栅电极 所述第二金属栅电极在所述翅片有源区的上表面具有第三厚度，在所述鳍有源区的所述侧壁处具有第四厚度，其中所述第三厚度小于所述第四厚度。

公开(公告)号：US20140054675A1

公开(公告)日：2014-02-27

申请号：US13945336

申请日：2013-07-18

申请人： Chae-Ho Kim ,  Sung-Hae Lee ,  Toshiro Nakanishi ,  Dong-Woo Kim

发明人： Sung-Hae LEE ,  Toshiro NAKANISHI ,  Dong-Woo KIM ,  Chae-Ho KIM

IPC分类号： H01L29/792 ,  H01L29/66

CPC分类号： H01L29/7926 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/66833

摘要： According to example embodiments, a vertical type semiconductor device includes a pillar structure on a substrate. The pillar structure includes a semiconductor pattern and a channel pattern. The semiconductor pattern includes an impurity region. A first word line structure faces the channel pattern and is horizontally extended while surrounding the pillar structure. A second word line structure has one side facing the impurity region of the semiconductor pattern and another side facing the substrate. A common source line is provided at a substrate portion adjacent to a sidewall end portion of the second word line structure.

摘要翻译： 根据示例性实施例，垂直型半导体器件包括在衬底上的柱结构。 柱结构包括半导体图案和沟道图案。 半导体图案包括杂质区域。 第一字线结构面向通道图案，并且在围绕柱结构的同时水平延伸。 第二字线结构具有面向半导体图案的杂质区域和面向衬底的另一侧的一侧。 在与第二字线结构的侧壁端部相邻的衬底部分处提供公共源极线。

公开(公告)号：US20120052672A1

公开(公告)日：2012-03-01

申请号：US13198143

申请日：2011-08-04

申请人： Toshiro Nakanishi ,  Choong-Man Lee

发明人： Toshiro Nakanishi ,  Choong-Man Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/11582

摘要： A method for fabricating a cell string includes forming an interlayer dielectric layer, a sacrificial layer, and a semiconductor pattern on a semiconductor substrate, such that the interlayer dielectric layer and the sacrificial layer are formed in a first direction parallel with the semiconductor substrate, and such that the semiconductor pattern is formed in a second direction perpendicular to the semiconductor substrate, forming an opening by patterning the interlayer dielectric layer and the sacrificial layer, filling the opening with a metal, and annealing the semiconductor pattern having the opening filled with the metal.

摘要翻译： 一种电池串的制造方法，包括在半导体基板上形成层间电介质层，牺牲层和半导体图案，使得层间绝缘层和牺牲层沿与半导体基板平行的第一方向形成，以及 使得半导体图案在垂直于半导体衬底的第二方向上形成，通过图案化层间电介质层和牺牲层形成开口，用金属填充开口，并且将具有填充有金属的开口的半导体图案退火 。