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    SEMICONDUCTOR LIGHT-EMITTING DEVICE
    1.
    发明申请
    SEMICONDUCTOR LIGHT-EMITTING DEVICE 审中-公开
    半导体发光器件

    公开(公告)号：US20160064611A1

    公开(公告)日：2016-03-03

    申请号：US14717942

    申请日：2015-05-20

    申请人： Pun Jae CHOI ,  Young Soo PARK ,  Yung Ho RYU ,  Tae Young PARK ,  Jin Gi HONG

    发明人： Pun Jae CHOI ,  Young Soo PARK ,  Yung Ho RYU ,  Tae Young PARK ,  Jin Gi HONG

    IPC分类号： H01L33/38 ,  H01L33/40 ,  H01L33/62 ,  H01L33/42

    CPC分类号： H01L33/382 ,  H01L33/405 ,  H01L33/42 ,  H01L33/62 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2924/00014

    摘要： A semiconductor light-emitting device includes a laminated semiconductor structure having a first surface and a second surface opposing each other, a first conductivity-type semiconductor layer and a second conductivity-type semiconductor layer respectively forming the first surface and the second surface, and an active layer. First and second electrodes are disposed on the first surface of the laminated semiconductor structure and the second surface of the laminated semiconductor structure, respectively. A connecting electrode extends to the first surface to be connected to the second electrode. A support substrate is disposed on the second electrode, and an insulating layer insulates the connecting electrode from the active layer and the first conductivity-type semiconductor layer.

    摘要翻译： 半导体发光器件包括具有彼此相对的第一表面和第二表面的层压半导体结构，分别形成第一表面和第二表面的第一导电类型半导体层和第二导电型半导体层， 活动层 第一和第二电极分别设置在叠层半导体结构的第一表面和层叠半导体结构的第二表面上。 连接电极延伸到要连接到第二电极的第一表面。 支撑基板设置在第二电极上，并且绝缘层使连接电极与有源层和第一导电型半导体层绝缘。

    Non-volatile memory devices including low-K dielectric gaps in substrates
    2.
    发明授权
    Non-volatile memory devices including low-K dielectric gaps in substrates 有权
    非易失性存储器件，包括衬底中的低K电介质间隙

    公开(公告)号：US08536652B2

    公开(公告)日：2013-09-17

    申请号：US13224427

    申请日：2011-09-02

    申请人： Bo-young Lee ,  Jong-wan Choi ,  Jin-gi Hong ,  Myoung-bum Lee

    发明人： Bo-young Lee ,  Jong-wan Choi ,  Jin-gi Hong ,  Myoung-bum Lee

    IPC分类号： H01L29/78

    CPC分类号： H01L21/764 ,  H01L27/11521 ,  H01L27/11568

    摘要： A method of manufacturing a non-volatile memory device, can be provided by forming a gate insulating layer and a gate conductive layer on a substrate that includes active regions that are defined by device isolation regions that include a carbon-containing silicon oxide layer. The gate conductive layer and the gate insulating layer can be sequentially etched to expose the carbon-containing silicon oxide layer. The carbon-containing silicon oxide layer can be wet-etched to recess a surface of the carbon-containing silicon oxide layer to below a surface of the substrate. Then, an interlayer insulating layer can be formed between the gate insulating layer and the gate conductive layer on the carbon-containing silicon oxide layer, where an air gap can be formed between the carbon-containing silicon oxide layer and the gate insulating layer.

    摘要翻译： 可以通过在包括由包含含碳氧化硅层的器件隔离区限定的有源区的衬底上形成栅极绝缘层和栅极导电层来提供制造非易失性存储器件的方法。 可以依次蚀刻栅极导电层和栅极绝缘层，以露出含碳氧化硅层。 可以对含碳氧化硅层进行湿蚀刻，以将含碳氧化硅层的表面凹入到衬底的表面下方。 然后，可以在含碳氧化硅层上的栅极绝缘层和栅极导电层之间形成层间绝缘层，其中可以在含碳氧化硅层和栅极绝缘层之间形成气隙。

    Chamber inserts and apparatuses for processing a substrate
    3.
    发明授权
    Chamber inserts and apparatuses for processing a substrate 有权
    腔体插入件和用于处理衬底的装置

    公开(公告)号：US08366827B2

    公开(公告)日：2013-02-05

    申请号：US11447933

    申请日：2006-06-07

    申请人： Jung-Hun Seo ,  Jin-Gi Hong ,  Kyung-Bum Koo ,  Yun-Ho Choi ,  Eun-Taeck Lee ,  Hyun Chul Kwun

    发明人： Jung-Hun Seo ,  Jin-Gi Hong ,  Kyung-Bum Koo ,  Yun-Ho Choi ,  Eun-Taeck Lee ,  Hyun Chul Kwun

    IPC分类号： C23C16/00 ,  C23F1/00 ,  H01L21/306

    CPC分类号： H01L21/68721 ,  C23C16/44 ,  C23C16/4408 ,  C23C16/45519 ,  C23C16/45591 ,  Y10T29/41

    摘要： Disclosed are chamber inserts and apparatuses using the chamber inserts. A chamber insert may include a cylindrical body portion including a top end portion and a bottom end portion, a first protruding portion extending outwardly from a first portion of the cylindrical body portion, the first portion positioned circumferentially along the cylindrical body portion and a second protruding portion extending outwardly from a second portion of the cylindrical body portion, the second portion positioned circumferentially along less than all of the cylindrical body portion. In another example, the chamber insert may include a cylindrical body portion including a top end portion and a bottom end portion, the cylindrical body portion including a slit and at least one hole, the slit and the at least one hole positioned circumferentially along the cylindrical body portion and a first protruding portion extending outwardly from a first portion of the cylindrical body portion.

    摘要翻译： 公开了使用腔室插入件的腔室插入件和装置。 腔室插入件可以包括包括顶端部分和底端部分的圆柱形主体部分，从圆柱形主体部分的第一部分向外延伸的第一突出部分，沿着圆柱形主体部分周向定位的第一部分和第二突出部分 该部分从圆柱形主体部分的第二部分向外延伸，第二部分沿着比圆柱形主体部分的全部圆周方向定位。 在另一示例中，腔室插入件可以包括包括顶端部分和底端部分的圆柱体部分，该圆柱形主体部分包括狭缝和至少一个孔，所述狭缝和至少一个孔沿着圆柱形 主体部分和从圆柱形主体部分的第一部分向外延伸的第一突出部分。

    Semiconductor device including a gate electrode of lower electrical resistance and method of manufacturing the same
    4.
    发明申请
    Semiconductor device including a gate electrode of lower electrical resistance and method of manufacturing the same 审中-公开
    包括具有较低电阻的栅电极的半导体器件及其制造方法

    公开(公告)号：US20080048274A1

    公开(公告)日：2008-02-28

    申请号：US11878096

    申请日：2007-07-20

    申请人： Jung-Hun Seo ,  Hyun-Young Kim ,  Jin-Gi Hong

    发明人： Jung-Hun Seo ,  Hyun-Young Kim ,  Jin-Gi Hong

    IPC分类号： H01L29/78 ,  H01L21/4763

    CPC分类号： H01L21/28061 ,  H01L29/4941

    摘要： A semiconductor device may include a gate insulating layer on a semiconductor substrate, a polysilicon layer doped with impurities on the gate insulating layer, an interface reaction preventing layer on the polysilicon layer, a barrier layer on the interface reaction preventing layer, and a conductive metal layer on the barrier layer. The interface reaction preventing layer may reduce or prevent the occurrence of a chemical interfacial reaction with the barrier layer, and the barrier layer may reduce or prevent the diffusion of impurities doped to the polysilicon layer. The interface reaction preventing layer may include a metal-rich metal silicide having a metal mole fraction greater than a silicon mole fraction, so that the interface reaction preventing layer may reduce or prevent the dissociation of the barrier layer at higher temperatures. Thus, a barrier characteristic of a poly-metal gate electrode may be improved and surface agglomerations may be reduced or prevented.

    摘要翻译： 半导体器件可以包括在半导体衬底上的栅极绝缘层，在栅极绝缘层上掺杂有杂质的多晶硅层，多晶硅层上的界面反应防止层，界面反应防止层上的阻挡层和导电金属 层在阻挡层上。 界面反应防止层可以减少或防止与阻挡层的化学界面反应的发生，并且阻挡层可以减少或防止掺杂到多晶硅层的杂质的扩散。 界面反应防止层可以包括具有大于硅摩尔分数的金属摩尔分数的富金属的金属硅化物，使得界面反应防止层可以降低或防止在较高温度下阻挡层的解离。 因此，可以改善多金属栅电极的阻挡特性，并且可以减少或防止表面团聚。

    Method of forming plasma and method of forming a layer using the same
    7.
    发明申请
    Method of forming plasma and method of forming a layer using the same 审中-公开
    形成等离子体的方法和使用其形成层的方法

    公开(公告)号：US20070042132A1

    公开(公告)日：2007-02-22

    申请号：US11450455

    申请日：2006-06-12

    申请人： Jung-Hun Seo ,  Young-Wook Park ,  JIn-Gi Hong ,  Kyung-Bum Koo ,  Eun-Taeck Lee ,  Yun-Ho Choi

    发明人： Jung-Hun Seo ,  Young-Wook Park ,  JIn-Gi Hong ,  Kyung-Bum Koo ,  Eun-Taeck Lee ,  Yun-Ho Choi

    IPC分类号： H05H1/24 ,  C03C15/00

    CPC分类号： C23C16/5096 ,  C23C16/14 ,  C23C16/34 ,  H01L21/28556 ,  H01L21/76841 ,  H01L21/76856

    摘要： A method of forming plasma used in a process of manufacturing a semiconductor device and a method of forming a layer for a semiconductor device using the plasma are disclosed. The plasma forming method includes forming a plasma region in a sealed space by supplying a plasma source gas into the sealed space at a first flow rate and maintaining the plasma region by supplying a plasma maintenance gas into the sealed space at a second flow rate higher than the first flow rate. The plasma source gas includes a first gas having a first atomic weight, and the plasma maintenance gas includes a second gas having a second atomic weight lower than the first atomic weight. The plasma source gas includes argon and the plasma maintenance gas includes helium. The method may further include forming the layer on a wafer by supplying a source gas into the sealed space.

    摘要翻译： 公开了一种在制造半导体器件的工艺中使用的形成等离子体的方法以及使用该等离子体形成半导体器件层的方法。 等离子体形成方法包括在密封空间中形成等离子体区域，通过以等于第一流量的方式将密封空间中的等离子体源气体以第一流量提供，并通过以等于或等于 第一流量。 等离子体源气体包括具有第一原子量的第一气体，等离子体维持气体包括具有比第一原子量低的第二原子量的第二气体。 等离子体源气体包括氩气，等离子体维持气体包括氦气。 该方法还可以包括通过将源气体供应到密封空间中在晶片上形成该层。

    METHODS OF FORMING NON-VOLATILE MEMORY DEVICES INCLUDING LOW-K DIELECTRIC GAPS IN SUBSTRATES AND DEVICES SO FORMED
    8.
    发明申请
    METHODS OF FORMING NON-VOLATILE MEMORY DEVICES INCLUDING LOW-K DIELECTRIC GAPS IN SUBSTRATES AND DEVICES SO FORMED 有权
    形成非易失性存储器件的方法，包括底片中的低K电介质GAPS和形成的器件

    公开(公告)号：US20120061763A1

    公开(公告)日：2012-03-15

    申请号：US13224427

    申请日：2011-09-02

    申请人： Bo-young LEE ,  Jong-wan Choi ,  Jin-gi Hong ,  Myoung-bum Lee

    发明人： Bo-young LEE ,  Jong-wan Choi ,  Jin-gi Hong ,  Myoung-bum Lee

    IPC分类号： H01L29/78 ,  H01L21/283

    CPC分类号： H01L21/764 ,  H01L27/11521 ,  H01L27/11568

    摘要： A method of manufacturing a non-volatile memory device, can be provided by forming a gate insulating layer and a gate conductive layer on a substrate that includes active regions that are defined by device isolation regions that include a carbon-containing silicon oxide layer. The gate conductive layer and the gate insulating layer can be sequentially etched to expose the carbon-containing silicon oxide layer. The carbon-containing silicon oxide layer can be wet-etched to recess a surface of the carbon-containing silicon oxide layer to below a surface of the substrate. Then, an interlayer insulating layer can be formed between the gate insulating layer and the gate conductive layer on the carbon-containing silicon oxide layer, where an air gap can be formed between the carbon-containing silicon oxide layer and the gate insulating layer.

    摘要翻译： 可以通过在包括由包含含碳氧化硅层的器件隔离区限定的有源区的衬底上形成栅极绝缘层和栅极导电层来提供制造非易失性存储器件的方法。 可以依次蚀刻栅极导电层和栅极绝缘层，以露出含碳氧化硅层。 可以对含碳氧化硅层进行湿蚀刻，以将含碳氧化硅层的表面凹入到衬底的表面下方。 然后，可以在含碳氧化硅层上的栅极绝缘层和栅极导电层之间形成层间绝缘层，其中可以在含碳氧化硅层和栅极绝缘层之间形成气隙。

    METHOD OF FORMING DEVICE ISOLATION LAYER AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    9.
    发明申请
    METHOD OF FORMING DEVICE ISOLATION LAYER AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE 审中-公开
    形成器件隔离层的方法和制造半导体器件的方法

    公开(公告)号：US20110003458A1

    公开(公告)日：2011-01-06

    申请号：US12829993

    申请日：2010-07-02

    申请人： Seung-jae Lee ,  Jin-gi Hong

    发明人： Seung-jae Lee ,  Jin-gi Hong

    IPC分类号： H01L21/762 ,  H01L21/28

    CPC分类号： H01L21/76232 ,  H01L29/66621

    摘要： Provided are a method of forming a device isolation layer and a method of fabricating a semiconductor device. The method includes: forming a first trench and a second trench in a substrate, wherein the second trench is connected to the first trench and has a width smaller than the first trench; forming a liner insulation layer in the second trench such that the liner insulation layer is buried in the second trench; and forming a gap fill insulation layer on the liner insulation layer such that the gap fill insulation layer is buried in the first trench.

    摘要翻译： 提供一种形成器件隔离层的方法和制造半导体器件的方法。 该方法包括：在衬底中形成第一沟槽和第二沟槽，其中第二沟槽连接到第一沟槽并具有小于第一沟槽的宽度; 在所述第二沟槽中形成衬垫绝缘层，使得所述衬垫绝缘层被埋在所述第二沟槽中; 以及在所述衬垫绝缘层上形成间隙填充绝缘层，使得所述间隙填充绝缘层被埋在所述第一沟槽中。