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    Providing dual work function doping
    1.
    发明授权
    Providing dual work function doping 失效
    提供双重功能掺杂

    公开(公告)号：US5937289A

    公开(公告)日：1999-08-10

    申请号：US3106

    申请日：1998-01-06

    申请人： Gary Bela Bronner ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  Carl J. Radens ,  William Robert Tonti

    发明人： Gary Bela Bronner ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  Carl J. Radens ,  William Robert Tonti

    IPC分类号： H01L21/225 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L21/8238

    CPC分类号： H01L21/28035 ,  H01L21/82345

    摘要： Dual work function doping is provided by doping a selected number of gate structures having self-aligned insulating layer on top of the structures through at least one side wall of the gate structures with a first conductivity type to thereby provide an array of gate structures whereby some are doped with the first conductivity type and others of the gate structures are doped with a second and different conductivity type. Also provided is an array of gate structures whereby the individual gate structures contain self-aligned insulating layer on their top portion and wherein some of the gate structures are doped with a first conductivity type and other of the gate structures are doped with a second and different conductivity type.

    摘要翻译： 通过在第一导电类型的栅极结构的至少一个侧壁上掺杂选定数量的具有自对准绝缘层的栅极结构的结构，从而提供栅极结构的阵列，从而提供一些 掺杂有第一导电类型，并且其他栅极结构被掺杂有第二和不同的导电类型。 还提供了栅极结构的阵列，其中各个栅极结构在其顶部部分上包含自对准的绝缘层，并且其中一些栅极结构被掺杂有第一导电类型，并且其他栅极结构被掺杂有第二和不同的 导电类型。

    Trench electrode with intermediate conductive barrier layer
    6.
    发明授权
    Trench electrode with intermediate conductive barrier layer 失效
    带中间导电阻挡层的沟槽电极

    公开(公告)号：US06236077B1

    公开(公告)日：2001-05-22

    申请号：US09295136

    申请日：1999-04-20

    申请人： Jeffrey P. Gambino ,  Rajarao Jammy ,  Jack A. Mandelman ,  Carl J. Radens

    发明人： Jeffrey P. Gambino ,  Rajarao Jammy ,  Jack A. Mandelman ,  Carl J. Radens

    IPC分类号： H01L27108

    CPC分类号： H01L27/10867 ,  H01L27/10861 ,  H01L29/66181 ,  H01L29/945

    摘要： Reduced scale trench capacitor structures of improved reliability and decreased series resistance are enabled by the creation and use of conductive barrier layers at intermediate points in the trench electrode structure. The conductive barrier layer is preferably either an intrinsically conductive compound barrier or a quantum conductive barrier. The capacitor structures are preferably characterized by a lower electrode region of very high dopant concentration.

    摘要翻译： 通过在沟槽电极结构的中间点处产生和使用导电阻挡层，可实现提高可靠性和降低串联电阻的缩小沟槽电容器结构。 导电阻挡层优选为本征导电化合物屏障或量子导电屏障。 电容器结构的特征在于具有非常高掺杂剂浓度的下电极区域。

    Low-resistance salicide fill for trench capacitors
    8.
    发明授权
    Low-resistance salicide fill for trench capacitors 失效
    沟槽电容器的低电阻自对准硅填料

    公开(公告)号：US06194755B1

    公开(公告)日：2001-02-27

    申请号：US09102471

    申请日：1998-06-22

    申请人： Jeffrey P. Gambino ,  Ulrike Gruening ,  Jack A. Mandelman ,  Carl J. Radens

    发明人： Jeffrey P. Gambino ,  Ulrike Gruening ,  Jack A. Mandelman ,  Carl J. Radens

    IPC分类号： H01L2120

    CPC分类号： H01L27/10861

    摘要： Trench capacitors are fabricated utilizing a method which results in a refractory metal salicide as a component of the trench electrode in a lower region of the trench. The salicide-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell layouts and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells.

    摘要翻译： 使用导致难熔金属硅化物作为沟槽的下部区域中的沟槽电极的部件的方法来制造沟槽电容器。 与具有类似尺寸的常规沟槽电极相比，含有自对接硅化物的沟槽电极显示出降低的串联电阻，从而可以减少接地规则存储单元布局和/或降低单元访问时间。 本发明的沟槽电容器特别可用作DRAM存储单元的组件。

    Dual work function gate conductors with self-aligned insulating cap
    9.
    发明授权
    Dual work function gate conductors with self-aligned insulating cap 失效
    具有自对准绝缘帽的双功能栅极导体

    公开(公告)号：US06274467B1

    公开(公告)日：2001-08-14

    申请号：US09327080

    申请日：1999-06-04

    申请人： Jeffrey P. Gambino ,  Louis L. Hsu ,  Jack A. Mandelman ,  Carl J. Radens ,  William R. Tonti

    发明人： Jeffrey P. Gambino ,  Louis L. Hsu ,  Jack A. Mandelman ,  Carl J. Radens ,  William R. Tonti

    IPC分类号： H01L2122

    CPC分类号： H01L21/28035 ,  H01L21/28052 ,  H01L21/32155 ,  H01L21/823842

    摘要： A dual work function gate conductor with a self-aligned insulating cap and method for forming the same is provided. Two diffusion regions are formed in a substrate and a gate stack is formed over the substrate between the diffusion regions. The gate stack includes a gate insulating layer formed on the substrate and a layer of polysilicon on top of the gate insulating layer. The polysilicon layer may be doped n-type remain intrinsic. A barrier layer is formed on top of the polysilicon layer and a dopant source layer is formed on top of the barrier layer. The barrier layer contains a p-type dopant. The gate stack is enclosed by an insulating cap so that a diffusion contact can be formed borderless to the gate. Activation of the dopant source layer to dope a polysilicon layer can be delayed until a desired time.

    摘要翻译： 提供一种具有自对准绝缘帽的双功能栅极导体及其形成方法。 在衬底中形成两个扩散区域，并且在扩散区域之间的衬底上形成栅叠层。 栅极堆叠包括形成在衬底上的栅极绝缘层和位于栅极绝缘层顶部的多晶硅层。 多晶硅层可以掺杂n型保持固有。 在多晶硅层的顶部形成阻挡层，并且在阻挡层的顶部上形成掺杂剂源层。 阻挡层含有p型掺杂剂。 栅极堆叠被绝缘盖封闭，使得扩散接触可以形成与栅极无边界。 激发掺杂剂源层以掺杂多晶硅层可以被延迟到期望的时间。