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    Dual work function gate conductors with self-aligned insulating cap
    5.
    发明授权
    Dual work function gate conductors with self-aligned insulating cap 失效
    具有自对准绝缘帽的双功能栅极导体

    公开(公告)号：US06274467B1

    公开(公告)日：2001-08-14

    申请号：US09327080

    申请日：1999-06-04

    申请人： Jeffrey P. Gambino ,  Louis L. Hsu ,  Jack A. Mandelman ,  Carl J. Radens ,  William R. Tonti

    发明人： Jeffrey P. Gambino ,  Louis L. Hsu ,  Jack A. Mandelman ,  Carl J. Radens ,  William R. Tonti

    IPC分类号： H01L2122

    CPC分类号： H01L21/28035 ,  H01L21/28052 ,  H01L21/32155 ,  H01L21/823842

    摘要： A dual work function gate conductor with a self-aligned insulating cap and method for forming the same is provided. Two diffusion regions are formed in a substrate and a gate stack is formed over the substrate between the diffusion regions. The gate stack includes a gate insulating layer formed on the substrate and a layer of polysilicon on top of the gate insulating layer. The polysilicon layer may be doped n-type remain intrinsic. A barrier layer is formed on top of the polysilicon layer and a dopant source layer is formed on top of the barrier layer. The barrier layer contains a p-type dopant. The gate stack is enclosed by an insulating cap so that a diffusion contact can be formed borderless to the gate. Activation of the dopant source layer to dope a polysilicon layer can be delayed until a desired time.

    摘要翻译： 提供一种具有自对准绝缘帽的双功能栅极导体及其形成方法。 在衬底中形成两个扩散区域，并且在扩散区域之间的衬底上形成栅叠层。 栅极堆叠包括形成在衬底上的栅极绝缘层和位于栅极绝缘层顶部的多晶硅层。 多晶硅层可以掺杂n型保持固有。 在多晶硅层的顶部形成阻挡层，并且在阻挡层的顶部上形成掺杂剂源层。 阻挡层含有p型掺杂剂。 栅极堆叠被绝缘盖封闭，使得扩散接触可以形成与栅极无边界。 激发掺杂剂源层以掺杂多晶硅层可以被延迟到期望的时间。

    Method of multi-port memory fabrication with parallel connected trench capacitors in a cell
    6.
    发明申请
    Method of multi-port memory fabrication with parallel connected trench capacitors in a cell 失效
    在单元中并联连接沟槽电容器的多端口存储器制造方法

    公开(公告)号：US20090176339A1

    公开(公告)日：2009-07-09

    申请号：US12316748

    申请日：2008-12-16

    申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Jack A. Mandelman ,  Carl J. Radens ,  Geng Wang

    发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Jack A. Mandelman ,  Carl J. Radens ,  Geng Wang

    IPC分类号： H01L21/8242

    CPC分类号： G11C8/16 ,  G11C11/405 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10861

    摘要： A method is provided for fabricating a multi-port memory in which a plurality of parallel connected capacitors are in a cell. A plurality of trench capacitors are formed which have capacitor dielectric layers extending along walls of the plurality of trenches, the plurality of trench capacitors having first capacitor plates and second capacitor plates opposite the capacitor dielectric layers from the first capacitor plates. The first capacitor plates are conductively tied together and the second capacitor plates are conductively tied together. In this way, the first capacitor plates are adapted to receive a same variable voltage and the second capacitor plates are adapted to receive a same fixed voltage.

    摘要翻译： 提供了一种用于制造其中多个并联电容器在单元中的多端口存储器的方法。 形成多个沟槽电容器，其具有沿多个沟槽的壁延伸的电容器电介质层，所述多个沟槽电容器具有第一电容器板和与第一电容器板相对的电容器电介质层的第二电容器板。 第一电容器板导电地连接在一起，并且第二电容器板被导电地连接在一起。 以这种方式，第一电容器板适于接收相同的可变电压，并且第二电容器板适于接收相同的固定电压。

    Structure and process for compact cell area in a stacked capacitor cell array
    7.
    发明授权
    Structure and process for compact cell area in a stacked capacitor cell array 失效
    叠层电容器阵列中紧凑单元面积的结构和工艺

    公开(公告)号：US06455886B1

    公开(公告)日：2002-09-24

    申请号：US09636564

    申请日：2000-08-10

    申请人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens

    发明人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens

    IPC分类号： H01L27108

    CPC分类号： H01L27/10876 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10894 ,  H01L29/66181

    摘要： A method for forming, and a structure for a semiconductor device having vertically-oriented transistors connected to stacked capacitor cells, wherein a contact area for the capacitors enables a compact cell. A vertically-oriented transistor is formed in a trough in a substrate above a buried bit line. The gate conductor may be formed in the trough above the buried bit line, with source and drain diffusions spaced along a sidewall of the trough. Isolation regions are formed in the semiconductor substrate to isolate the transistors. Word lines are formed above the surface of the semiconductor substrate in a direction perpendicular to the direction of the buried bit lines. A capacitor contact is formed above the surface of the semiconductor substrate at a contact area of an active region between adjacent word lines. The active region is rhomboid in shape, enabling a low capacitor contact resistance, a small bit line and word line pitch, and consequently, a compact capacitor cell.

    摘要翻译： 一种用于形成的方法，以及具有连接到层叠电容器单元的垂直取向的晶体管的半导体器件的结构，其中电容器的接触面积使得能够实现紧凑的电池。 垂直取向的晶体管形成在掩埋位线上方的衬底的槽中。 栅极导体可以形成在掩埋位线上方的槽中，源极和漏极扩散沿着槽的侧壁间隔开。 在半导体衬底中形成隔离区以隔离晶体管。 在与掩埋位线的方向垂直的方向上在半导体衬底的表面上形成字线。 在相邻字线之间的有源区域的接触区域处，在半导体衬底的表面上方形成电容器触点。 有源区域是菱形形状，能够实现低电容器接触电阻，小位线和字线间距，从而实现紧凑的电容器单元。

    Vertical MOSFET
    9.
    发明授权
    Vertical MOSFET 失效
    垂直MOSFET

    公开(公告)号：US06414347B1

    公开(公告)日：2002-07-02

    申请号：US09790011

    申请日：2001-02-09

    申请人： Ramachandra Divakaruni ,  Heon Lee ,  Jack A. Mandelman ,  Carl J. Radens ,  Jai-Hoon Sim

    发明人： Ramachandra Divakaruni ,  Heon Lee ,  Jack A. Mandelman ,  Carl J. Radens ,  Jai-Hoon Sim

    IPC分类号： H01L2972

    CPC分类号： H01L27/10864 ,  H01L21/2255 ,  H01L21/26586 ,  H01L27/10841 ,  H01L29/66666 ,  H01L29/7827

    摘要： An improved process for making a vertical MOSFET structure comprising: A method of forming a semiconductor memory cell array structure comprising: providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer planarized to a top surface of a trench top oxide on the overlying silicon substrate; forming a recess in the gate conductor layer below the top surface of the silicon substrate; implanting N-type dopant species through the recess at an angle to form doping pockets in the array P-well; depositing an oxide layer into the recess and etching said oxide layer to form spacers on sidewalls of the recess; depositing a gate conductor material into said recess and planarizing said gate conductor to said top surface of the trench top oxide.

    摘要翻译： 一种用于制造垂直MOSFET结构的改进方法，包括：一种形成半导体存储单元阵列结构的方法，包括：提供垂直MOSFET DRAM单元结构，其具有平坦化到覆盖硅上的沟槽顶部氧化物的顶表面的沉积栅极导体层 基质; 在所述硅衬底的顶表面下方的所述栅极导体层中形成凹部; 以一定角度注入N型掺杂剂物质通过凹槽形成阵列P-阱中的掺杂凹坑; 将氧化物层沉积到所述凹部中并蚀刻所述氧化物层以在所述凹部的侧壁上形成间隔物; 将栅极导体材料沉积到所述凹部中并将所述栅极导体平坦化到所述沟槽顶部氧化物的所述顶表面。

    Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays
    10.
    发明授权
    Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays 有权
    在EDRAM阵列中形成双功能高性能支持MOSFET的方法

    公开(公告)号：US06261894B1

    公开(公告)日：2001-07-17

    申请号：US09706492

    申请日：2000-11-03

    申请人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens

    发明人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens

    IPC分类号： H01L218234

    CPC分类号： H01L27/10864 ,  H01L27/10894 ,  H01L27/10897

    摘要： Methods of preparing dual workfunction high-performance support metal oxide semiconductor field effect transistor (MOSFETs)/embedded dynamic random access (EDRAM) arrays are provided. The methods describe herein reduce the number of deep-UV masks used in the forming memory structure, decouple the support and arraying processing steps, provide salicided gates, source/drain regions and bitlines, and provide, in some instances, local interconnects at no additional processing costs. Dual workfunction high-performance support MOSFETs/ EDRAM arrays having a gate conductor guard ring and/or local interconnections are also provided.

    摘要翻译： 提供双功能功能高性能支持金属氧化物半导体场效应晶体管（MOSFET）/嵌入式动态随机存取（EDRAM）阵列的方法。 这里描述的方法减少了在形成存储器结构中使用的深UV掩模的数量，解耦支持和排列处理步骤，提供盐化栅极，源极/漏极区域和位线，并且在一些情况下提供局部互连， 加工成本。 还提供了双功能功能的高性能支持具有栅极导体保护环和/或局部互连的MOSFET / EDRAM阵列。