公开(公告)号：US20120313647A1

公开(公告)日：2012-12-13

申请号：US13156836

申请日：2011-06-09

申请人： GARY DALE CARPENTER ,  Alan James Drake ,  Eren Kursun ,  Phillip John Restle

发明人： GARY DALE CARPENTER ,  Alan James Drake ,  Eren Kursun ,  Phillip John Restle

IPC分类号： G01R27/28

CPC分类号： G11C29/025 ,  G01R31/2882 ,  G11C7/10 ,  G11C29/50012 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and system for an infrastructure for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A critical path monitor circuit (infrastructure) is configured to launch a signal from a launch point in a first layer, the first layer being a first circuit. The infrastructure is further configured to create an electrical path to a capture point. The signal is launched from the launch point in the first layer. A performance characteristic of the electrical path is measured, resulting in a measurement, wherein the measurement is indicative of a performance of the first layer when stacked with a second layer in a 3D stack without actually stacking the first and the second layers in the 3D stack, the second layer being a second circuit.

摘要翻译： 在说明性实施例中提供了用于基于性能的芯片到芯片堆叠的基础设施的方法和系统。 关键路径监控电路（基础设施）被配置为从第一层中的发射点发射信号，第一层是第一电路。 基础设施还被配置为创建到捕获点的电路径。 信号从第一层的发射点发射。 测量电路径的性能特征，从而进行测量，其中测量表示当与3D堆叠中的第二层堆叠时的第一层的性能，而不会在3D堆叠中实际堆叠第一层和第二层 ，第二层是第二电路。

公开(公告)号：US20120266125A1

公开(公告)日：2012-10-18

申请号：US13087464

申请日：2011-04-15

申请人： Gary Dale Carpenter ,  Alan James Drake ,  Eren Kursun ,  Phillip John Restle

发明人： Gary Dale Carpenter ,  Alan James Drake ,  Eren Kursun ,  Phillip John Restle

IPC分类号： G06F17/50

CPC分类号： H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method, system, and computer program product for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A first candidate chip is selected from a set of candidate chips for stacking, each candidate chip in the set of candidate chips including an integrated circuit. A part of a 3D performance determinant is activated in the first candidate chip. A value of a performance parameter is measured for a set of operating conditions. A stacked performance value is computed for the first candidate chip using the value. A subset of the set of candidate chips is stacked in a stack, the subset including the first candidate chip, such that a combined value of the performance parameter for the subset when stacked in a first order is within a defined range of values for the performance parameter.

摘要翻译： 在说明性实施例中提供了用于基于性能的芯片到芯片堆叠的方法，系统和计算机程序产品。 从用于堆叠的候选芯片的集合中选择第一候选芯片，所述候选芯片组中的每个候选芯片包括集成电路。 在第一候选芯片中激活3D性能决定因素的一部分。 对于一组操作条件测量性能参数的值。 使用该值计算第一候选芯片的堆叠性能值。 所述候选芯片组的子集被堆叠在堆叠中，所述子集包括第一候选芯片，使得当以第一顺序堆叠时子集的性能参数的组合值在所述性能的值的确定范围内 参数。

公开(公告)号：US09251913B2

公开(公告)日：2016-02-02

申请号：US13156836

申请日：2011-06-09

申请人： Gary Dale Carpenter ,  Alan James Drake ,  Eren Kursun ,  Phillip John Restle

发明人： Gary Dale Carpenter ,  Alan James Drake ,  Eren Kursun ,  Phillip John Restle

IPC分类号： G01R27/28 ,  G11C29/02 ,  G01R31/28 ,  G11C7/10 ,  H01L25/065 ,  G11C29/50

CPC分类号： G11C29/025 ,  G01R31/2882 ,  G11C7/10 ,  G11C29/50012 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and system for an infrastructure for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A critical path monitor circuit (infrastructure) is configured to launch a signal from a launch point in a first layer, the first layer being a first circuit. The infrastructure is further configured to create an electrical path to a capture point. The signal is launched from the launch point in the first layer. A performance characteristic of the electrical path is measured, resulting in a measurement, wherein the measurement is indicative of a performance of the first layer when stacked with a second layer in a 3D stack without actually stacking the first and the second layers in the 3D stack, the second layer being a second circuit.

摘要翻译： 在说明性实施例中提供了用于基于性能的芯片到芯片堆叠的基础设施的方法和系统。 关键路径监控电路（基础设施）被配置为从第一层中的发射点发射信号，第一层是第一电路。 基础设施还被配置为创建到捕获点的电路径。 信号从第一层的发射点发射。 测量电路径的性能特征，从而进行测量，其中测量表示当与3D堆叠中的第二层堆叠时的第一层的性能，而不会在3D堆叠中实际堆叠第一层和第二层 ，第二层是第二电路。

公开(公告)号：US08543959B2

公开(公告)日：2013-09-24

申请号：US13087464

申请日：2011-04-15

申请人： Gary Dale Carpenter ,  Alan James Drake ,  Eren Kursun

发明人： Gary Dale Carpenter ,  Alan James Drake ,  Eren Kursun

IPC分类号： G06F17/50

CPC分类号： H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method, system, and computer program product for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A first candidate chip is selected from a set of candidate chips for stacking, each candidate chip in the set of candidate chips including an integrated circuit. A part of a 3D performance determinant is activated in the first candidate chip. A value of a performance parameter is measured for a set of operating conditions. A stacked performance value is computed for the first candidate chip using the value. A subset of the set of candidate chips is stacked in a stack, the subset including the first candidate chip, such that a combined value of the performance parameter for the subset when stacked in a first order is within a defined range of values for the performance parameter.

摘要翻译： 在说明性实施例中提供了用于基于性能的芯片到芯片堆叠的方法，系统和计算机程序产品。 从用于堆叠的候选芯片的集合中选择第一候选芯片，所述候选芯片组中的每个候选芯片包括集成电路。 在第一候选芯片中激活3D性能决定因素的一部分。 对于一组操作条件测量性能参数的值。 使用该值计算第一候选芯片的堆叠性能值。 所述候选芯片组的子集被堆叠在堆叠中，所述子集包括第一候选芯片，使得当以第一顺序堆叠时子集的性能参数的组合值在所述性能的值的确定范围内 参数。

公开(公告)号：US08677613B2

公开(公告)日：2014-03-25

申请号：US12774223

申请日：2010-05-20

申请人： Eren Kursun ,  Philip G. Emma ,  Jude A. Rivers

发明人： Eren Kursun ,  Philip G. Emma ,  Jude A. Rivers

IPC分类号： H05K3/30

CPC分类号： H01L23/147 ,  H01L21/4803 ,  H01L23/13 ,  H01L23/5382 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/18 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K3/30 ,  H05K3/465 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49137 ,  Y10T29/49146 ,  H01L2924/00

摘要： Enhanced modularity in heterogeneous three-dimensional computer processing chip stacks includes a method of manufacture. The method includes preparing a host layer and integrating the host layer with at least one other layer in the stack. The host layer is prepared by forming cavities on the host layer for receiving chips pre-configured with heterogeneous properties relative to each other, disposing the chips in corresponding cavities on the host layer, and joining the chips to respective surfaces of the cavities thereby forming an element having a smooth surface with respect to the host layer and the chips.

摘要翻译： 异构三维计算机处理芯片堆栈中的增强的模块化包括制造方法。 该方法包括准备主机层并将主机层与栈中的至少一个其他层集成。 主体层通过在主体层上形成空腔来制备，用于接收相对于彼此预先配置有非均匀性质的芯片，将芯片设置在主体层上的相应空腔中，以及将芯片连接到空腔的相应表面，从而形成 元件具有相对于主体层和芯片的平滑表面。

公开(公告)号：US20130331996A1

公开(公告)日：2013-12-12

申请号：US13494047

申请日：2012-06-12

申请人： Thomas Brunschwiler ,  Eren Kursun ,  Gary W. Maier

发明人： Thomas Brunschwiler ,  Eren Kursun ,  Gary W. Maier

IPC分类号： G05D23/00 ,  G05D7/00

CPC分类号： G06F1/20 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

摘要： A computer-implemented method, system, and article of manufacture for optimizing heat transfer in a 3-D chip-stack. The method includes the steps of: receiving a heat-removal effectiveness parameter for a plurality of channel-region areas in the chip-stack, receiving at least one of a flow value and temperature value for at least two of the channel-region areas, comparing the received values for different channel-region areas, and adjusting a flow rate of a liquid flowing to at least one of the two channel-region areas based on the heat-removal effectiveness parameter of the channel-region area receiving the adjustment and the results of the comparison step, where at least one step is carried out using a computer device.

摘要翻译： 用于优化3-D芯片堆叠中的热传递的计算机实现的方法，系统和制品。 该方法包括以下步骤：接收码片堆叠中的多个信道区域区域的散热有效性参数，接收至少两个信道区域区域的流量值和温度值中的至少一个， 比较不同通道区域的接收值，并且基于接收调整的通道区域区域的散热效率参数来调节流入两个通道区域区域中的至少一个的液体的流量， 比较步骤的结果，其中使用计算机设备执行至少一个步骤。

公开(公告)号：US08571847B2

公开(公告)日：2013-10-29

申请号：US12727984

申请日：2010-03-19

申请人： Chen-Yong Cher ,  Paul W. Coteus ,  Alan Gara ,  Eren Kursun ,  David P. Paulsen ,  Brian A. Schuelke ,  John E. Sheets, II ,  Shurong Tian

发明人： Chen-Yong Cher ,  Paul W. Coteus ,  Alan Gara ,  Eren Kursun ,  David P. Paulsen ,  Brian A. Schuelke ,  John E. Sheets, II ,  Shurong Tian

IPC分类号： G06G7/75

CPC分类号： G06F1/3203 ,  G06F1/206 ,  G06F1/3237 ,  G06F11/24 ,  Y02D10/128 ,  Y02D10/16

摘要： A processor-implemented method for improving efficiency of a static core turn-off in a multi-core processor with variation, the method comprising: conducting via a simulation a turn-off analysis of the multi-core processor at the multi-core processor's design stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's design stage includes a first output corresponding to a first multi-core processor core to turn off; conducting a turn-off analysis of the multi-core processor at the multi-core processor's testing stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's testing stage includes a second output corresponding to a second multi-core processor core to turn off; comparing the first output and the second output to determine if the first output is referring to the same core to turn off as the second output; outputting a third output corresponding to the first multi-core processor core if the first output and the second output are both referring to the same core to turn off.

摘要翻译： 一种用于提高多核处理器中的静态核心关断的效率的处理器实现的方法，所述方法包括：通过模拟在多核处理器的设计处进行多核处理器的关断分析 其中所述多核处理器的设计阶段的所述多核处理器的关断分析包括对应于第一多核处理器核的第一输出关闭; 在多核处理器的测试阶段对多核处理器进行关断分析，其中多核处理器的测试阶段的多核处理器的关断分析包括对应于第二多核处理器的第二多输出 核心处理器核心关闭; 比较第一输出和第二输出以确定第一输出是否指相同的磁芯作为第二输出关闭; 如果第一输出和第二输出均指向相同的核来关闭，则输出对应于第一多核处理器核心的第三输出。

公开(公告)号：US20120268909A1

公开(公告)日：2012-10-25

申请号：US13535660

申请日：2012-06-28

申请人： Philip G. Emma ,  Eren Kursun ,  Jude A. Rivers

发明人： Philip G. Emma ,  Eren Kursun ,  Jude A. Rivers

IPC分类号： H05K7/02

CPC分类号： H01L23/147 ,  H01L21/4803 ,  H01L23/13 ,  H01L23/5382 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/18 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K3/30 ,  H05K3/465 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49137 ,  Y10T29/49146 ,  H01L2924/00

摘要： A three-dimensional computer processing chip stack that includes a host layer disposed on at least one other layer in the stack. The host layer includes cavities formed thereon for receiving chips pre-configured with heterogeneous properties relative to each other. The cavities are formed to accommodate the heterogeneous properties of the chips. The chips are joined to respective surfaces of the cavities, thereby forming an element having a smooth surface with respect to the host layer and the chips.

摘要翻译： 一种三维计算机处理芯片堆叠，其包括布置在堆叠中的至少一个其他层上的主机层。 主体层包括形成在其上的空腔，用于接收预先配置有相对于彼此的异质特性的芯片。 形成空腔以适应芯片的不均匀性质。 芯片被连接到空腔的相应表面，从而形成相对于主体层和芯片具有平滑表面的元件。

公开(公告)号：US20120254400A1

公开(公告)日：2012-10-04

申请号：US13077578

申请日：2011-03-31

申请人： Madhusudan K. Iyengar ,  Vinod Kamath ,  Eren Kursun ,  Roger R. Schmidt

发明人： Madhusudan K. Iyengar ,  Vinod Kamath ,  Eren Kursun ,  Roger R. Schmidt

IPC分类号： G06F15/173

CPC分类号： G06F9/5094 ,  Y02D10/22

摘要： A system to improve operation of a data center with heterogeneous computing clouds may include monitoring components to track data center climate controls and individual heterogeneous computing clouds' operating parameters within the data center. The system may also include a controller that regulates the individual heterogeneous computing clouds and data center climate controls based upon data generated by the monitoring components to improve the operating performance of the individual heterogeneous computing clouds as well as the operating performance of the data center. The system may further include spilling computing clouds to receive excess workload of an individual heterogeneous computing cloud without violating individual heterogeneous computing clouds contracts.

摘要翻译： 改进具有异构计算云的数据中心运行的系统可能包括监视组件以跟踪数据中心气候控制和数据中心内的个别异构计算云运行参数。 该系统还可以包括控制器，其基于由监视组件生成的数据来调节各个异构计算云和数据中心气候控制，以改善各个异构计算云的操作性能以及数据中心的操作性能。 该系统可以进一步包括溢出计算云以接收单个异构计算云的额外的工作量，而不违反个别的异构计算云合同。

公开(公告)号：US20120173036A1

公开(公告)日：2012-07-05

申请号：US12984096

申请日：2011-01-04

申请人： Chen-Yong Cher ,  Wilfried E. Haensch ,  Eren Kursun ,  David R. Motschman

发明人： Chen-Yong Cher ,  Wilfried E. Haensch ,  Eren Kursun ,  David R. Motschman

IPC分类号： G05D23/19

CPC分类号： G06F1/3234 ,  G06F1/206

摘要： A mechanism is provided for minimizing reliability problems in a three-dimensional (3D)) integrated circuit. A set of sensors are interrogated for current data. A direction of force and a magnitude of the force are determined based on the current data for each sensor in the set of sensors for each of one or more directions between the sensor and at least one neighboring sensor thereby forming a set of forces. Each of the set of forces is used to identify one or more points of stress that are at or above the predetermined force threshold. Responsive to identifying at least one point of stress that is at or above the predetermined force threshold, one or more temperature actuation actions are initiated in order to reduce at least one point of stress in the region where the at least one point of stress is identified.

摘要翻译： 提供了用于最小化三维（3D））集成电路中的可靠性问题的机制。 一组传感器被询问用于当前数据。 基于用于传感器和至少一个相邻传感器之间的一个或多个方向中的每一个的传感器组中的每个传感器的当前数据来确定力的方向和力的大小，从而形成一组力。 所述一组力中的每一个用于识别处于或高于预定力阈值的一个或多个应力点。 响应于识别处于或高于预定力阈值的至少一个应力点，启动一个或多个温度致动动作，以便在识别出至少一个应力点的区域中减少至少一个应力点 。