公开(公告)号：US5449638A

公开(公告)日：1995-09-12

申请号：US254532

申请日：1994-06-06

申请人： Gary Hong ,  Chen-Chiu Hsue ,  H. J. Wu ,  Lawrence Y. Lin

发明人： Gary Hong ,  Chen-Chiu Hsue ,  H. J. Wu ,  Lawrence Y. Lin

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76251 ,  Y10S148/012 ,  Y10S148/135

摘要： A method for forming a thin, uniform top silicon layer using bonded-wafer SOI technology is described. A dielectric layer is formed on a first surface of a first silicon substrate. A trench is formed in a first surface of a second silicon substrate. A polishing stopper is formed in the trench. A second dielectric layer with a smooth top surface is formed over the polishing stopper and over the first surface of the second silicon substrate. The smooth top surface of the second dielectric layer of the second silicon substrate is bonded to the dielectric layer of the first silicon substrate. Material is removed from the exposed surface of the second silicon substrate to form the silicon layer with well-controlled thickness, having a top surface co-planar with the polishing stopper.

摘要翻译： 描述了使用接合晶片SOI技术形成薄的均匀顶部硅层的方法。 介电层形成在第一硅衬底的第一表面上。 在第二硅衬底的第一表面中形成沟槽。 在沟槽中形成抛光止动件。 在抛光止动器上方并在第二硅衬底的第一表面上形成具有平滑顶表面的第二电介质层。 第二硅衬底的第二电介质层的平滑顶表面结合到第一硅衬底的电介质层。 从第二硅衬底的暴露表面去除材料以形成具有良好控制厚度的硅层，其具有与抛光止挡件共面的顶表面。

公开(公告)号：US5998251A

公开(公告)日：1999-12-07

申请号：US975492

申请日：1997-11-21

申请人： H. J. Wu ,  Shih-Wei Sun ,  Jacob Chen ,  Tri-Rung Yew

发明人： H. J. Wu ,  Shih-Wei Sun ,  Jacob Chen ,  Tri-Rung Yew

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10808

摘要： An integrated circuit device having both an array of logic circuits and an array of embedded DRAM circuits is provided using a process that avoids some of the most significant processing challenges for embedded DRAM integration. Transfer FETs and wiring lines are provided for the embedded DRAM circuits and FETs are provided for the logic portions of the device in an initial phase of the process. The gate electrodes and source/drain regions of the logic FETs are subjected to a salicide process at this initial phase and a thick planarized oxide layer is provided over both the embedded DRAM regions and the logic circuit regions. Capacitors and logic interconnects are next formed using common etching, titanium nitride deposition and tungsten deposition steps. Contact vias are formed to expose each of the source drain regions of the DRAM transfer FETs and to expose select conductors within the logic circuits. A titanium nitride layer is deposited over the device and within the various contact vias through the planarized oxide layer. A capacitor dielectric layer is provided over the device and then the capacitor dielectric layer is selectively removed from at least the contact vias that become bit line contacts and logic interconnects. A layer of tungsten is deposited and patterned to provide upper capacitor electrodes and to complete the bit line contacts and logic interconnects. This first level tungsten layer also can provide bit line wiring. The 1/2 V.sub.cc potential for the upper capacitor electrodes can be provided to the circuit using a level of interconnect wiring also used by the logic circuits.

摘要翻译： 使用避免嵌入式DRAM集成的一些最重要的处理挑战的过程来提供具有逻辑电路阵列和嵌入式DRAM电路阵列的集成电路器件。 为嵌入式DRAM电路提供转移FET和布线，并且在该过程的初始阶段为器件的逻辑部分提供FET。 逻辑FET的栅极电极和源极/漏极区域在该初始阶段经受自对准硅化物处理，并且在嵌入式DRAM区域和逻辑电路区域上均设置厚平坦化的氧化物层。 接下来使用常规蚀刻，氮化钛沉积和钨沉积步骤形成电容器和逻辑互连。 形成接触通孔以暴露DRAM传输FET的每个源极漏极区域并暴露在逻辑电路内的选择导体。 氮化钛层通过平坦化的氧化物层沉积在器件上并在各种接触孔内。 在器件上提供电容器介电层，然后至少选择性地从形成位线接触和逻辑互连的接触孔中去除电容器介质层。 沉积钨层并图案化以提供上层电容器电极并完成位线接触和逻辑互连。 该第一级钨层也可以提供位线布线。 上电容器电极的+ E，fra 1/2 + EE Vcc电位可以使用也由逻辑电路使用的互连布线的电平提供给电路。

公开(公告)号：US5399531A

公开(公告)日：1995-03-21

申请号：US628437

申请日：1990-12-17

申请人： H. J. Wu

发明人： H. J. Wu

IPC分类号： B65G49/07 ,  H01L21/00 ,  H01L21/677 ,  H01L21/68 ,  B65G35/00 ,  G06F15/46

CPC分类号： H01L21/67724 ,  H01L21/67017 ,  H01L21/67727 ,  H01L21/67736 ,  Y10S414/136 ,  Y10S414/137 ,  Y10S414/139 ,  Y10T29/41

摘要： A manufacturing system and method for processing semiconductor wafers through a plurality of processing stations that perform manufacturing operations on wafers includes a plurality of processing stations, each of which are capable of performing at least one processing operation on a wafer, each of the processing stations having a controlled environment for processing the wafers, and a branched tunnel joined and communicating with the controlled environment. A means is provided for maintaining a clean environment in the tunnel. Within the tunnel there are provided a plurality of guided transport vehicles adapted to travel between the process stations. A plurality of wafer carriers, each adapted to support a single wafer and be carried by the transport vehicles, are part of the system.

摘要翻译： 通过在晶片上进行制造操作的多个处理站来处理半导体晶片的制造系统和方法包括多个处理站，每个处理站能够对晶片执行至少一个处理操作，每个处理站具有 用于处理晶片的受控环境，以及连接并与受控环境通信的分支隧道。 提供了一种在隧道内保持清洁环境的手段。 在隧道内设置有适于在处理站之间行进的多个被引导的运输车辆。 多个晶片载体，各自适于支撑单个晶片并由运输车辆承载，是系统的一部分。

公开(公告)号：US6071658A

公开(公告)日：2000-06-06

申请号：US24911

申请日：1998-02-17

申请人： H. J. Wu ,  Shyi-Long Shy

发明人： H. J. Wu ,  Shyi-Long Shy

IPC分类号： G03F1/68 ,  G03F1/76 ,  G03F1/78 ,  G03F7/20 ,  H01J37/317 ,  H01L21/027 ,  G03F9/00 ,  G03C5/00

CPC分类号： B82Y10/00 ,  B82Y40/00 ,  G03F1/36 ,  G03F7/2059 ,  H01J37/3174 ,  H01J2237/31769

摘要： A proximity effect correction method for mask production by integrating the electron beam proximity effect correction method and the optical proximity effect correction method such that the problems of having too large a computer-aided design pattern data file during mask production and using the mask to transfer the image to the wafer by a stepper is solved. The correction method of this invention comprises the steps of providing a pattern for forming on a mask, and then dividing the mask area into a plurality of first area patches and a plurality of second area patches, wherein each first area patch contains part of the whole pattern while each second area patch does not contain any pattern. Next, according to pattern density and light contrast, the amount of exposure by electron beam is adjusted such that electron beam proximity effect and optical proximity effect are corrected forming a corrected pattern. Finally, using the corrected pattern, an electron beam exposure operation is carried out to form the mask.

摘要翻译： 通过对电子束邻近效应校正方法和光学邻近效应校正方法进行积分的掩模制造的邻近效应校正方法，使得在掩模制作期间存在计算机辅助设计图案数据文件太大的问题并且使用掩模来传送 解决了通过步进器对晶片的图像。 本发明的校正方法包括以下步骤：提供用于在掩模上形成的图案，然后将掩模区域划分成多个第一区域斑块和多个第二区域斑块，其中每个第一区域斑块包含整体的一部分 而每个第二个区域补丁不包含任何模式。 接下来，根据图案密度和光对比度，调整电子束的曝光量，从而校正形成校正图案的电子束邻近效应和光学邻近效应。 最后，使用校正的图案，进行电子束曝光操作以形成掩模。

公开(公告)号：US6048762A

公开(公告)日：2000-04-11

申请号：US55577

申请日：1998-04-06

申请人： Liang-Choo Hsia ,  H. J. Wu

发明人： Liang-Choo Hsia ,  H. J. Wu

IPC分类号： H01L21/285 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/8244

CPC分类号： H01L27/10852 ,  H01L21/28512 ,  H01L27/10808

摘要： A method of fabricating an embedded dynamic random access memory. Using the method of dual damascence, by forming patterning only one dielectric layer, the contact windows with different depth are formed. In addition, the metal layer formed within the metal connecting regions are used as interconnects without further process.

摘要翻译： 一种制造嵌入式动态随机存取存储器的方法。 使用双重阻力的方法，通过仅形成图案化的一个电介质层，形成具有不同深度的接触窗口。 此外，形成在金属连接区域内的金属层用作互连而不进一步处理。