公开(公告)号：US5796141A

公开(公告)日：1998-08-18

申请号：US784588

申请日：1997-01-23

申请人： Ruei-Ling Lin ,  Ching-Hsiang Hsu ,  Gary Hong

发明人： Ruei-Ling Lin ,  Ching-Hsiang Hsu ,  Gary Hong

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A compact contactless trenched flash memory array for semiconductor EEPROM devices is disclosed. The flash memory array comprises a number of memory cell units. Each of the cell units comprises a body line, source and drain regions and a stacked gate constructed over a silicon wafer substrate. The source and drain regions are buried regions and the body line is isolated by the surrounding buried source/drain regions and trenches formed to cut deep down to the substrate of the wafer. The stacked gate includes a first polysilicon layer, an oxide-nitride-oxide configuration, a second polysilicon layer, a pad oxide layer and a nitride layer. The source and drain buried regions sandwiches the body line, and the stacked gate substantially sits directly atop the body line. The flash memory array is free from the serious problem of short channel effect.

摘要翻译： 公开了一种用于半导体EEPROM器件的紧凑型非接触式沟槽闪存阵列。 闪存阵列包括多个存储单元单元。 每个单元单元包括体线，源极和漏极区域以及在硅晶片衬底上构造的堆叠栅极。 源极和漏极区域是掩埋区域，并且主体线被周围的掩埋源极/漏极区域和形成为深切割到晶片的衬底的沟槽隔离。 层叠栅极包括第一多晶硅层，氧化物 - 氮化物 - 氧化物构造，第二多晶硅层，焊盘氧化物层和氮化物层。 源极和漏极掩埋区域夹着体线，并且堆叠的栅极基本上直接位于身体线上方。 闪存阵列没有短通道效应的严重问题。

公开(公告)号：US5726070A

公开(公告)日：1998-03-10

申请号：US622692

申请日：1996-03-26

申请人： Gary Hong ,  Ching-Hsiang Hsu

发明人： Gary Hong ,  Ching-Hsiang Hsu

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H01L29/788 ,  H01L21/8247

CPC分类号： H01L21/28185 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7882 ,  H01L21/28194

摘要： A process for forming an EEPROM having silicon rich tunnel oxide is disclosed. This oxide is used in the formation of flash EEPROMs and results in high tunneling current at low voltages. The oxide also results in EEPROMs having good endurance. A layer of silicon enriched with oxygen is formed between the substrate and the insulating layer separating the substrate from the floating gate.

摘要翻译： 公开了一种形成具有富硅隧道氧化物的EEPROM的工艺。 该氧化物用于形成快速EEPROM，并在低电压下产生高隧穿电流。 氧化物还导致具有良好耐久性的EEPROM。 在衬底和将衬底与浮动栅极分离的绝缘层之间形成富含氧的一层硅。

公开(公告)号：US5885868A

公开(公告)日：1999-03-23

申请号：US789202

申请日：1997-01-24

申请人： Ruei-Ling Lin ,  Ching-Hsiang Hsu ,  Gary Hong

发明人： Ruei-Ling Lin ,  Ching-Hsiang Hsu ,  Gary Hong

IPC分类号： H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7883 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203

摘要： A process for fabricating compact contactless flash memory array for semiconductor EEPROM devices having a number of memory cell units is disclosed. Field oxide layers for the flash memory array are first grown over the surface of an SOI wafer. Gate oxide layers are then grown. Floating gates are then formed by patterning the first polysilicon layer. Source/drain buried bitlines for the flash memory array are formed. A first BPSG (borophosphosilicate glass) layer is deposited and then reflown and etched back. An oxide-nitride-oxide layer is formed. A second polysilicon layer is deposited with in-situ dope. A WSi.sub.x layer then forms. Stacked gates for the flash array are formed by patterning into the formed oxide-nitride-oxide, second polysilicon and WSi.sub.x layers. The stacked gates are then covered with a second BPSG layer. Contact openings for the source/drain buried lines are formed. Metal lines leading into the contact openings are then formed for interconnecting the memory cells in the flash memory array with peripheral control circuits of the semiconductor EEPROM devices.

摘要翻译： 公开了一种用于制造具有多个存储单元单元的半导体EEPROM器件的紧凑型非接触式闪速存储器阵列的方法。 闪存阵列的场氧化物层首先在SOI晶片的表面上生长。 然后生长栅极氧化物层。 然后通过图案化第一多晶硅层形成浮栅。 形成闪存阵列的源/漏掩埋位线。 沉积第一个BPSG（硼磷硅酸盐玻璃）层，然后退回并回蚀刻。 形成氧化物 - 氮化物 - 氧化物层。 第二多晶硅层沉积有原位涂料。 然后形成一个WSix层。 用于闪存阵列的堆叠栅极通过图案化形成为形成的氧化物 - 氮化物 - 氧化物，第二多晶硅和WSix层。 堆叠的栅极然后用第二个BPSG层覆盖。 形成用于源极/漏极掩埋线的接触开口。 然后形成导入接触开口的金属线，以将闪存阵列中的存储单元与半导体EEPROM器件的外围控制电路互连。

公开(公告)号：US5851879A

公开(公告)日：1998-12-22

申请号：US786907

申请日：1997-01-22

申请人： Ruei-Ling Lin ,  Ching-Hsiang Hsu ,  Gary Hong

发明人： Ruei-Ling Lin ,  Ching-Hsiang Hsu ,  Gary Hong

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method for fabricating compact contactless trenched flash memory array for semiconductor EEPROM devices is disclosed. The flash memory array comprises a number of memory cell units. Each of the cell units comprises a body line, source and drain regions and a stacked gate constructed over a silicon wafer substrate. The source and drain regions are buried regions and the body line is isolated by the surrounding buried source/drain regions and trenches formed to cut deep down to the substrate of the wafer. The stacked gate includes a first polysilicon layer, an oxide-nitride-oxide configuration, a second polysilicon layer, a pad oxide layer and a nitride layer. The source and drain buried regions sandwiches the body line, and the stacked gate substantially sits directly atop the body line. The flash memory array is free from the serious problem of short channel effect.

摘要翻译： 公开了一种用于制造用于半导体EEPROM器件的紧凑型非接触式沟槽闪存阵列的方法。 闪存阵列包括多个存储单元单元。 每个单元单元包括体线，源极和漏极区域以及在硅晶片衬底上构造的堆叠栅极。 源极和漏极区域是掩埋区域，并且主体线被周围的掩埋源极/漏极区域和形成为深切割到晶片的衬底的沟槽隔离。 层叠栅极包括第一多晶硅层，氧化物 - 氮化物 - 氧化物构造，第二多晶硅层，焊盘氧化物层和氮化物层。 源极和漏极掩埋区域夹着体线，并且堆叠的栅极基本上直接位于身体线上方。 闪存阵列没有短通道效应的严重问题。

公开(公告)号：US5796142A

公开(公告)日：1998-08-18

申请号：US786908

申请日：1997-01-22

申请人： Ruei-Ling Lin ,  Ching-Hsiang Hsu ,  Gary Hong

发明人： Ruei-Ling Lin ,  Ching-Hsiang Hsu ,  Gary Hong

IPC分类号： H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/788

CPC分类号： H01L29/7883 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203

摘要： A compact contactless flash memory array for semiconductor EEPROM devices having a number of memory cell units. Field oxide layers for the flash memory array are first grown over the surface of an SOI wafer. Gate oxide layers are then grown. Floating gates are then formed by patterning the first polysilicon layer. Source/drain buried bitlines for the flash memory array are formed. A first BPSG (borophosphosilicate glass) layer is deposited and then reflown and etched back. An oxide-nitride-oxide layer is formed. A second polysilicon layer is deposited with in-situ dope. A WSi.sub.x layer then forms. Stacked gates for the flash array are formed by patterning into the formed oxide-nitride-oxide, second polysilicon and WSi.sub.x layers. The stacked gates are then covered with a second BPSG layer. Contact openings for the source/drain buried lines are formed. Metal lines leading into the contact openings are then formed for interconnecting the memory cells in the flash memory array with peripheral control circuits of the semiconductor EEPROM devices.

摘要翻译： 一种用于具有多个存储单元单元的半导体EEPROM器件的紧凑型非接触式闪存阵列。 闪存阵列的场氧化物层首先在SOI晶片的表面上生长。 然后生长栅极氧化物层。 然后通过图案化第一多晶硅层形成浮栅。 形成闪存阵列的源/漏掩埋位线。 沉积第一个BPSG（硼磷硅酸盐玻璃）层，然后退回并回蚀刻。 形成氧化物 - 氮化物 - 氧化物层。 第二多晶硅层沉积有原位涂料。 然后形成一个WSix层。 用于闪存阵列的堆叠栅极通过图案化形成为形成的氧化物 - 氮化物 - 氧化物，第二多晶硅和WSix层。 堆叠的栅极然后用第二个BPSG层覆盖。 形成用于源极/漏极掩埋线的接触开口。 然后形成导入接触开口的金属线，以将闪存阵列中的存储单元与半导体EEPROM器件的外围控制电路互连。

公开(公告)号：US06750673B1

公开(公告)日：2004-06-15

申请号：US10249443

申请日：2003-04-10

申请人： Heng-Sheng Huang ,  Gary Hong ,  Shih-Chieh Lin ,  Yueh-Hsun Lee

发明人： Heng-Sheng Huang ,  Gary Hong ,  Shih-Chieh Lin ,  Yueh-Hsun Lee

IPC分类号： G01R3126

CPC分类号： H01L22/12

摘要： A first compensation factor, a second compensation factor and a third compensation factor are provided to improve a capacitance-voltage (C-V) method for measuring an effective channel length of a metal-oxide-semiconductor field effect transistor (MOSFET), and an overlap length of a gate and a source and a drain of the transistor. The first compensation factor is calculated by measuring two unit length gate capacitances of the transistor. The second compensation factor is calculated by measuring two unit length overlap capacitances of the transistor. The third compensation factor is a ratio of the second compensation factor to the first compensation factor.

摘要翻译： 提供第一补偿因子，第二补偿因子和第三补偿因子以改善用于测量金属氧化物半导体场效应晶体管（MOSFET）的有效沟道长度的电容电压（CV）方法，以及重叠长度 的晶体管的栅极和源极和漏极。 通过测量晶体管的两个单位长度栅极电容来计算第一个补偿因子。 通过测量晶体管的两个单位长度重叠电容来计算第二个补偿因子。 第三补偿因子是第二补偿因子与第一补偿因子的比率。

公开(公告)号：US06720267B1

公开(公告)日：2004-04-13

申请号：US10249149

申请日：2003-03-19

申请人： Anchor Chen ,  Gary Hong

发明人： Anchor Chen ,  Gary Hong

IPC分类号： H01L21311

CPC分类号： B81C1/0015 ,  B81B2201/047

摘要： A cantilever beam type micro-electromechanical system (MEMS) is formed on a substrate. Two first electrodes are formed in a first dielectric layer on the substrate and a waveguide line is formed between the first electrodes. A patterned sacrificial layer and an arm layer are formed on the substrate. Two second electrodes and a second dielectric layer are formed in the arm layer, and an optical grating is formed in the second dielectric layer. Finally, a cap layer is formed on the substrate, and the patterned sacrificial layer is removed.

摘要翻译： 在基板上形成悬臂梁型微机电系统（MEMS）。 两个第一电极形成在衬底上的第一电介质层中，并且在第一电极之间形成波导线。 在基板上形成图案化的牺牲层和臂层。 在臂层中形成两个第二电极和第二电介质层，并且在第二电介质层中形成光栅。 最后，在衬底上形成覆盖层，去除图案化的牺牲层。

公开(公告)号：US06350677B1

公开(公告)日：2002-02-26

申请号：US09630869

申请日：2000-08-02

申请人： Joe Ko ,  Gary Hong

发明人： Joe Ko ,  Gary Hong

IPC分类号： H01L214763

CPC分类号： H01L29/6659 ,  H01L21/28518 ,  H01L29/665

摘要： A method of forming a self-aligned silicide layer. A planarization process is performed to form a gate with a planar top surface. Due to the planar top surface of the gate, the reactivity and the uniformity of thickness of the subsequently formed silicide layer on the top surface of the gate are improved, such that the resistance of the silicide is reduced, and the performance of the device is improved.

摘要翻译： 一种形成自对准硅化物层的方法。 进行平面化处理以形成具有平坦顶表面的栅极。 由于栅极的平面顶表面，栅极顶表面上随后形成的硅化物层的反应性和厚度的均匀性得到改善，使得硅化物的电阻降低，并且器件的性能为 改进。

公开(公告)号：US06284597B1

公开(公告)日：2001-09-04

申请号：US09273067

申请日：1999-03-19

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21336

CPC分类号： H01L27/11521

摘要： A method of fabricating a flash memory is described. First, a shallow trench isolation structure is formed on the substrate, so that the surface of the shallow trench isolation structure is projected above the surface of the substrate. Then, a spacer is formed on the sidewall of the shallow trench isolation structure, which projects above the surface of the substrate. With the spacer serving as a mask, a gate oxide layer not covered by the spacer is etched to expose the substrate. By thermal oxidation, a self-aligned tunneling oxide layer is formed on the exposed substrate. The spacer is then removed. A floating gate is formed on the tunneling oxide layer. In addition, a dielectric layer and a control gate are formed on the floating gate in sequence, thus completing the flash memory structure.

摘要翻译： 描述制造闪速存储器的方法。 首先，在衬底上形成浅沟槽隔离结构，使得浅沟槽隔离结构的表面突出到衬底的表面上方。 然后，在浅沟槽隔离结构的侧壁上形成间隔物，其在基板的表面上方突出。 利用间隔物作为掩模，蚀刻未被间隔物覆盖的栅极氧化物层以露出衬底。 通过热氧化，在曝光的基底上形成自对准的隧道氧化物层。 然后移除间隔物。 在隧道氧化物层上形成浮栅。 此外，依次在浮动栅极上形成电介质层和控制栅极，从而完成闪存结构。

公开(公告)号：US06274477B1

公开(公告)日：2001-08-14

申请号：US09336554

申请日：1999-06-19

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L2128

CPC分类号： H01L21/7682

摘要： A method of fabricating a conductive line structure. A first dielectric layer is formed on a substrate. A conductive layer is formed on the first dielectric layer. The conductive layer is patterned to form an opening in the conductive layer. The opening exposes a portion of the first dielectric layer. A conformal stop layer is formed over the substrate. The conformal stop layer is conformal to the conductive layer. An oxide layer is formed in the opening. The oxide layer does not completely fill the opening. A portion of a sidewall of the opening is exposed. A spacer is formed on the exposed sidewall of the opening. The oxide layer is removed. A second dielectric layer is formed over the substrate to fill the opening. A void is formed in the second dielectric layer in the opening.

摘要翻译： 一种制造导线结构的方法。 在基板上形成第一电介质层。 在第一电介质层上形成导电层。 将导电层图案化以在导电层中形成开口。 开口暴露第一电介质层的一部分。 在衬底上形成共形停止层。 保形停止层与导电层共形。 在开口中形成氧化物层。 氧化层不完全填满开口。 开口侧壁的一部分露出。 间隔件形成在开口的暴露的侧壁上。 去除氧化物层。 第二介质层形成在衬底上以填充开口。 在开口中的第二介电层中形成空隙。