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    Method of manufacturing a dielectric layer for a silicon-oxide-nitride-oxide-silicon (SONOS) type devices
    2.
    发明授权
    Method of manufacturing a dielectric layer for a silicon-oxide-nitride-oxide-silicon (SONOS) type devices 有权
    制造氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型器件的介质层的方法

    公开(公告)号：US06818558B1

    公开(公告)日：2004-11-16

    申请号：US10185470

    申请日：2002-06-28

    申请人： Manuj Rathor ,  Krishnaswamy Ramkumar ,  Fred Jenne ,  Loren Lancaster

    发明人： Manuj Rathor ,  Krishnaswamy Ramkumar ,  Fred Jenne ,  Loren Lancaster

    IPC分类号： H01L21311

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/7882

    摘要： A method of forming a charge storing layer is disclosed. According to an embodiment, a method may include the steps of forming a first portion of a charge storing layer with a first gas flow rate ratio (step 102), forming at least a second portion of the charge storing layer by changing to a second gas flow rate ratio that is different than the first gas flow rate ratio (step 104), and forming at least a third portion of the charge storing layer by changing to a third gas flow rate ratio that is different than the second gas flow rate ratio (step 106).

    摘要翻译： 公开了形成电荷存储层的方法。 根据实施例，一种方法可以包括以第一气体流速比形成电荷存储层的第一部分（步骤102）的步骤，通过改变到第二气体形成电荷存储层的至少第二部分 流量比与第一气体流量比不同（步骤104），并且通过改变到与第二气体流量比不同的第三气体流量比形成至少第三部分的电荷存储层（ 步骤106）。

    Low voltage flash memory and method for manufacturing same
    3.
    发明申请
    Low voltage flash memory and method for manufacturing same 失效
    低压闪存及其制造方法

    公开(公告)号：US20020033502A1

    公开(公告)日：2002-03-21

    申请号：US09947419

    申请日：2001-09-05

    申请人： Anam Semiconductor, Inc.

    发明人： Jung-Wook Shin ,  Jae-Seung Kim ,  Hong-Seub Kim

    IPC分类号： H01L029/788

    CPC分类号： H01L29/7883 ,  H01L21/28194 ,  H01L21/28273 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7882

    摘要： A memory comprises a gate oxide layer formed on a semiconductor substrate; an ion trap region formed in a corner portion of the gate oxide layer; a floating gate formed on the gate oxide layer; a dielectric layer formed on the floating gate; a control gate formed on the dielectric layer; a spacer provided along side walls of a formed gate; an LDD formed under the spacer on the semiconductor substrate, the LDD being doped at a low concentration with impurities; and a source/drain region formed on an element region of the semiconductor substrate contacting the LDD, the source/drain region being doped at a high concentration with impurities. In one embodiment, the ion trap region is formed by performing ion injection into a corner portion of the gate oxide after the gate, including the control gate and the floating gate, is formed.

    摘要翻译： 存储器包括形成在半导体衬底上的栅氧化层; 形成在栅极氧化物层的角部的离子阱区域; 形成在栅极氧化物层上的浮栅; 形成在浮动栅极上的电介质层; 形成在所述电介质层上的控制栅极; 沿着形成的门的侧壁设置的间隔件; 在半导体衬底上的间隔物之下形成的LDD，LDD以低浓度掺杂杂质; 以及源极/漏极区域，形成在与LDD接触的半导体衬底的元件区域上，源/漏区域以高浓度掺杂杂质。 在一个实施例中，在形成包括控制栅极和浮置栅极的栅极之后，通过对栅极氧化物的角部进行离子注入来形成离子阱区域。

    Three-dimensional direct-write EEPROM arrays and fabrication methods
    4.
    发明授权
    Three-dimensional direct-write EEPROM arrays and fabrication methods 失效
    三维直写EEPROM阵列及制作方法

    公开(公告)号：US5467305A

    公开(公告)日：1995-11-14

    申请号：US850734

    申请日：1992-03-12

    申请人： Claude L. Bertin ,  Donelli J. DiMaria ,  Makoto Miyakawa ,  Yoshinori Sakaue

    发明人： Claude L. Bertin ,  Donelli J. DiMaria ,  Makoto Miyakawa ,  Yoshinori Sakaue

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C14/00

    CPC分类号： H01L27/11556 ,  H01L27/115 ,  H01L29/7882

    摘要： A three-dimensional memory cell, suitable for electrically erasable programmable read only memories (EEPROMS), which has direct-write cell capability is disclosed. The memory cell is utilized in the fabrication of non-volatile, direct-write EEPROM arrays with high integration density. A typical EEPROM array includes a plurality of elongated shallow trenches formed in a semiconductor substrate. Multiple direct-write EEPROM cells are disposed within each elongated trench such that each EEPROM cell shares a recall gate and a program gate with another cell in the same trench. Preferably, a silicon rich dielectric (such as silicon rich oxide) disposed between each floating gate and its associated programming and recall gates. Both common source diffusion and isolated source diffusion embodiments are disclosed. Further, various fabrication methods for the direct-write EEPROM arrays presented are described.

    摘要翻译： 公开了一种适用于具有直写单元能力的电可擦除可编程只读存储器（EEPROMS）的三维存储单元。 存储单元用于制造具有高集成度密度的非易失性直写EEPROM阵列。 典型的EEPROM阵列包括形成在半导体衬底中的多个细长的浅沟槽。 多个直写EEPROM单元被布置在每个细长沟槽内，使得每个EEPROM单元与相同沟槽中的另一个单元共享回调门和编程门。 优选地，设置在每个浮动栅极与其相关联的编程和调用栅极之间的富硅电介质（例如富氧氧化物）。 公开了源极扩散和隔离源扩散实施例。 此外，描述了所呈现的用于直写EEPROM阵列的各种制造方法。

    Non-volatile RAM device
    6.
    发明授权
    Non-volatile RAM device 失效
    非易失性RAM设备

    公开(公告)号：US4471471A

    公开(公告)日：1984-09-11

    申请号：US336463

    申请日：1981-12-31

    申请人： Donelli J. DiMaria

    发明人： Donelli J. DiMaria

    IPC分类号： G11C14/00 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792 ,  G11C11/24

    CPC分类号： G11C14/00 ,  H01L29/7882

    摘要： Juxtaposing, on a common p-type substrate, an array of field effect transistor memory cells each including a random access memory dynamic RAM device comprising a floating gate portion and a storage node, and each including also a non-volatile unit comprising a double electron injector structure (DEIS) adjacent the floating gate portion, but remote from the storage node, provides a simple, low current dynamic random access memory array with non-volatile restart capability in case of power interruption.The non-volatile unit in each memory cell shares the control gate and substrate in common with the dynamic RAM device and thus shares access to the floating gate but is remote from the storage node. Situated between the floating gate and the substrate is a silicon-rich DEIS stack. During normal operation, the device functions as a dynamic RAM device. When non-volatile storage is required, electrons are written into the floating gate by raising the voltage on the control gate. This injects electrons into an insulating layer in the DEIS; the electrons flow to the floating gate where they are stored indefinitely. Subsequent write and erase operations are carried out by applying an appropriately polarized voltage pulse to the control gate electrode, moving electrons with respect to the floating gate portion of the RAM device.

    摘要翻译： 每个场效应晶体管存储单元阵列在公共p型衬底上并置，每个场效应晶体管存储单元包括一个包括浮动栅极部分和存储节点的随机存取存储器动态RAM器件，并且每个还包括一个包含双电子 与浮动栅极部分相邻但远离存储节点的喷射器结构（DEIS）在电力中断的情况下提供具有非易失性重启能力的简单的低电流动态随机存取存储器阵列。 每个存储器单元中的非易失性单元与动态RAM设备共用控制栅极和衬底，从而共享对浮动栅极的访问，但是远离存储节点。 位于浮动栅极和基板之间的是富含硅的DEIS堆叠。 在正常操作期间，该设备用作动态RAM设备。 当需要非易失性存储时，通过提高控制栅极上的电压将电子写入浮置栅极。 这将电子注入到DEIS中的绝缘层中; 电子流到浮动栅极，无限期地存储在其中。 通过向控制栅电极施加适当极化的电压脉冲，相对于RAM器件的浮动栅极部分移动电子来执行随后的写入和擦除操作。

    Three terminal electrically erasable programmable read only memory
    7.
    发明授权
    Three terminal electrically erasable programmable read only memory 失效
    三端电可擦除可编程只读存储器

    公开(公告)号：US4336603A

    公开(公告)日：1982-06-22

    申请号：US160530

    申请日：1980-06-18

    申请人： Harish N. Kotecha ,  Francis W. Wiedman, III

    发明人： Harish N. Kotecha ,  Francis W. Wiedman, III

    IPC分类号： G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

    CPC分类号： H01L29/7882 ,  G11C16/0425

    摘要： A memory system is provided for charging and discharging small cells each of which has only three terminals with a charge injector controlled by a low single polarity voltage. Each of the cells includes a transistor having a current carrying electrode and a floating gate, with a control gate arranged so that a first capacitor is serially connected with a second capacitor between the current carrying electrode and the control gate, with one of the capacitors having a substantially larger capacitance than that of the other capacitor and with the other capacitor including a charge injector. The common point between the first and second capacitors is connected to the floating gate. The charge injector may include a single graded or stepped composition region or two such regions disposed near opposite faces or plates of the other capacitor, or more particularly the injector may include silicon rich regions near one or both faces of a layer of silicon dioxide.

    摘要翻译： 提供了一种存储系统，用于对小型电池进行充电和放电，每个小电池仅具有三个端子，电荷注入器由低的单极性电压控制。 每个单元包括具有载流电极和浮置栅极的晶体管，控制栅极布置成使得第一电容器与载流电极和控制栅极之间的第二电容器串联连接，其中一个电容器具有 比另一个电容器的电容大得多，而另一个电容器包括电荷注入器。 第一和第二电容器之间的共同点连接到浮动栅极。 电荷注入器可以包括设置在另一个电容器的相对面或平板附近的单个渐变或阶梯组成区域或两个这样的区域，或者更具体地，注射器可以包括在二氧化硅层的一个或两个面附近的富硅区域。

    NONVOLATILE MEMORY DEVICE
    8.
    发明申请
    NONVOLATILE MEMORY DEVICE 审中-公开

    公开(公告)号：US20180308854A1

    公开(公告)日：2018-10-25

    申请号：US15769629

    申请日：2016-08-25

    申请人： National Institute of Advanced Industrial Science and Technology

    发明人： Noriyuki Miyata

    IPC分类号： H01L27/11521 ,  H01L29/788 ,  H01L29/51

    CPC分类号： H01L28/56 ,  H01L27/11521 ,  H01L29/517 ,  H01L29/66181 ,  H01L29/7882 ,  H01L29/792 ,  H01L29/94

    摘要： A nonvolatile memory device can be manufactured without adding any major modification to a structure and component elements of a conventional MOS type silicon device, and is realized without deteriorating an electrical characteristic of an insulating-film/semiconductor interface and on the basis of a new operational principle. The nonvolatile memory device 10 is a capacitor configured by a metal electrode 16, two kinds of insulating films 13 and 15, and an interface structure of an insulating film 12/semiconductor 11, and has a MIS structure of providing a monolayer-level O-M1-O layer 14 to an insulating-film 13/semiconductor 15 interface. The nonvolatile memory device 10 realizes a nonvolatile information storage operation by changing strength or polarities of interface dipoles induced near the O-M1-O layer 14 through electrical stimulation applied from a gate electrode.