公开(公告)号：US06750673B1

公开(公告)日：2004-06-15

申请号：US10249443

申请日：2003-04-10

申请人： Heng-Sheng Huang ,  Gary Hong ,  Shih-Chieh Lin ,  Yueh-Hsun Lee

发明人： Heng-Sheng Huang ,  Gary Hong ,  Shih-Chieh Lin ,  Yueh-Hsun Lee

IPC分类号： G01R3126

CPC分类号： H01L22/12

摘要： A first compensation factor, a second compensation factor and a third compensation factor are provided to improve a capacitance-voltage (C-V) method for measuring an effective channel length of a metal-oxide-semiconductor field effect transistor (MOSFET), and an overlap length of a gate and a source and a drain of the transistor. The first compensation factor is calculated by measuring two unit length gate capacitances of the transistor. The second compensation factor is calculated by measuring two unit length overlap capacitances of the transistor. The third compensation factor is a ratio of the second compensation factor to the first compensation factor.

摘要翻译： 提供第一补偿因子，第二补偿因子和第三补偿因子以改善用于测量金属氧化物半导体场效应晶体管（MOSFET）的有效沟道长度的电容电压（CV）方法，以及重叠长度 的晶体管的栅极和源极和漏极。 通过测量晶体管的两个单位长度栅极电容来计算第一个补偿因子。 通过测量晶体管的两个单位长度重叠电容来计算第二个补偿因子。 第三补偿因子是第二补偿因子与第一补偿因子的比率。

公开(公告)号：US5350698A

公开(公告)日：1994-09-27

申请号：US55567

申请日：1993-05-03

申请人： Heng-Sheng Huang ,  Kun-Luh Chen ,  Gary Hong

发明人： Heng-Sheng Huang ,  Kun-Luh Chen ,  Gary Hong

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L21/265 ,  B05D3/06 ,  C23C16/00

CPC分类号： H01L29/6659 ,  H01L21/28035 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/7833

摘要： A new method of forming a self-aligning polysilicon gate is described. A gate silicon oxide is formed over a silicon substrate. A polysilicon layer is formed over the gate oxide. A native silicon oxide layer is formed over the polysilicon layer. A second polysilicon layer is formed over the native silicon oxide layer. Additional alternating layers of polysilicon and native silicon oxide are formed as desired. The wafer is annealed at between about 800.degree. to 1000.degree. C. This causes, it is believed, the silicon oxide gas from the multiple native silicon oxide layers to be exhausted resulting in the removal of all silicon oxide layers. A polycide layer is formed overlying the multiple polysilicon layers, if desired. Conventional lithography and etching techniques are used to form a gate. Ions are implanted into the substrate to form source/drain regions, using the multilayer gate as a mask. Rapid thermal annealing activates the impurities. A dielectric layer is deposited followed by conventional metallization techniques to complete construction of the integrated circuit.

摘要翻译： 描述形成自对准多晶硅栅极的新方法。 在硅衬底上形成栅氧化硅。 在栅极氧化物上形成多晶硅层。 在多晶硅层上形成天然硅氧化物层。 在天然氧化硅层上形成第二多晶硅层。 根据需要形成多晶硅和天然氧化硅的附加交替层。 晶片在约800℃至1000℃之间退火。据信，来自多个天然氧化硅层的氧化硅气体被排出，导致所有氧化硅层的去除。 如果需要，多晶硅层形成在多个多晶硅层上。 常规的光刻和蚀刻技术被用于形成栅极。 使用多层栅极作为掩模将离子注入到衬底中以形成源极/漏极区域。 快速热退火激活杂质。 沉积介电层，然后通过常规金属化技术来完成集成电路的构造。

公开(公告)号：US06720267B1

公开(公告)日：2004-04-13

申请号：US10249149

申请日：2003-03-19

申请人： Anchor Chen ,  Gary Hong

发明人： Anchor Chen ,  Gary Hong

IPC分类号： H01L21311

CPC分类号： B81C1/0015 ,  B81B2201/047

摘要： A cantilever beam type micro-electromechanical system (MEMS) is formed on a substrate. Two first electrodes are formed in a first dielectric layer on the substrate and a waveguide line is formed between the first electrodes. A patterned sacrificial layer and an arm layer are formed on the substrate. Two second electrodes and a second dielectric layer are formed in the arm layer, and an optical grating is formed in the second dielectric layer. Finally, a cap layer is formed on the substrate, and the patterned sacrificial layer is removed.

摘要翻译： 在基板上形成悬臂梁型微机电系统（MEMS）。 两个第一电极形成在衬底上的第一电介质层中，并且在第一电极之间形成波导线。 在基板上形成图案化的牺牲层和臂层。 在臂层中形成两个第二电极和第二电介质层，并且在第二电介质层中形成光栅。 最后，在衬底上形成覆盖层，去除图案化的牺牲层。

公开(公告)号：US06350677B1

公开(公告)日：2002-02-26

申请号：US09630869

申请日：2000-08-02

申请人： Joe Ko ,  Gary Hong

发明人： Joe Ko ,  Gary Hong

IPC分类号： H01L214763

CPC分类号： H01L29/6659 ,  H01L21/28518 ,  H01L29/665

摘要： A method of forming a self-aligned silicide layer. A planarization process is performed to form a gate with a planar top surface. Due to the planar top surface of the gate, the reactivity and the uniformity of thickness of the subsequently formed silicide layer on the top surface of the gate are improved, such that the resistance of the silicide is reduced, and the performance of the device is improved.

摘要翻译： 一种形成自对准硅化物层的方法。 进行平面化处理以形成具有平坦顶表面的栅极。 由于栅极的平面顶表面，栅极顶表面上随后形成的硅化物层的反应性和厚度的均匀性得到改善，使得硅化物的电阻降低，并且器件的性能为 改进。

公开(公告)号：US06284597B1

公开(公告)日：2001-09-04

申请号：US09273067

申请日：1999-03-19

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21336

CPC分类号： H01L27/11521

摘要： A method of fabricating a flash memory is described. First, a shallow trench isolation structure is formed on the substrate, so that the surface of the shallow trench isolation structure is projected above the surface of the substrate. Then, a spacer is formed on the sidewall of the shallow trench isolation structure, which projects above the surface of the substrate. With the spacer serving as a mask, a gate oxide layer not covered by the spacer is etched to expose the substrate. By thermal oxidation, a self-aligned tunneling oxide layer is formed on the exposed substrate. The spacer is then removed. A floating gate is formed on the tunneling oxide layer. In addition, a dielectric layer and a control gate are formed on the floating gate in sequence, thus completing the flash memory structure.

摘要翻译： 描述制造闪速存储器的方法。 首先，在衬底上形成浅沟槽隔离结构，使得浅沟槽隔离结构的表面突出到衬底的表面上方。 然后，在浅沟槽隔离结构的侧壁上形成间隔物，其在基板的表面上方突出。 利用间隔物作为掩模，蚀刻未被间隔物覆盖的栅极氧化物层以露出衬底。 通过热氧化，在曝光的基底上形成自对准的隧道氧化物层。 然后移除间隔物。 在隧道氧化物层上形成浮栅。 此外，依次在浮动栅极上形成电介质层和控制栅极，从而完成闪存结构。

公开(公告)号：US06274477B1

公开(公告)日：2001-08-14

申请号：US09336554

申请日：1999-06-19

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L2128

CPC分类号： H01L21/7682

摘要： A method of fabricating a conductive line structure. A first dielectric layer is formed on a substrate. A conductive layer is formed on the first dielectric layer. The conductive layer is patterned to form an opening in the conductive layer. The opening exposes a portion of the first dielectric layer. A conformal stop layer is formed over the substrate. The conformal stop layer is conformal to the conductive layer. An oxide layer is formed in the opening. The oxide layer does not completely fill the opening. A portion of a sidewall of the opening is exposed. A spacer is formed on the exposed sidewall of the opening. The oxide layer is removed. A second dielectric layer is formed over the substrate to fill the opening. A void is formed in the second dielectric layer in the opening.

摘要翻译： 一种制造导线结构的方法。 在基板上形成第一电介质层。 在第一电介质层上形成导电层。 将导电层图案化以在导电层中形成开口。 开口暴露第一电介质层的一部分。 在衬底上形成共形停止层。 保形停止层与导电层共形。 在开口中形成氧化物层。 氧化层不完全填满开口。 开口侧壁的一部分露出。 间隔件形成在开口的暴露的侧壁上。 去除氧化物层。 第二介质层形成在衬底上以填充开口。 在开口中的第二介电层中形成空隙。

公开(公告)号：US06268241B1

公开(公告)日：2001-07-31

申请号：US09408152

申请日：1999-09-29

申请人： Hwi-Huang Chen ,  Gary Hong

发明人： Hwi-Huang Chen ,  Gary Hong

IPC分类号： H01L218249

CPC分类号： H01L21/28052 ,  H01L29/665

摘要： A method for forming a self-aligned silicide (or called salicide) structure in IC fabrication is described. This method is characterized by the step of making the top surface of a polysilicon-based structure into a rugged surface, which allows the subsequently formed salicide structure over the rugged surface of the polysilicon-based structure to have an increased surface area and thus have a reduced sheet resistance when compared to the prior art. By this method, the first step is to prepare a semiconductor substrate, after which an oxide layer is formed over the substrate. Next, a polysilicon-based structure is formed over the oxide layer, and then the exposed surface of the polysilicon-based structure is reshaped into a rugged surface. Subsequently, a silicide layer is formed over the rugged surface of the polysilicon-based structure, which serves as the intended salicide structure.

摘要翻译： 描述了在IC制造中形成自对准硅化物（或称为自对准硅化物）结构的方法。 该方法的特征在于使基于多晶硅的结构的顶表面成为粗糙表面的步骤，其允许在多晶硅基结构的粗糙表面上随后形成的自对准硅化物结构具有增加的表面积，因此具有 与现有技术相比降低了薄层电阻。 通过该方法，第一步是制备半导体衬底，然后在衬底上形成氧化物层。 接下来，在氧化物层上形成多晶硅基结构，然后将多晶硅基结构的暴露表面重新成形为粗糙的表面。 随后，在多晶硅基结构的粗糙表面上形成硅化物层，其用作预期的自对准硅化物结构。

公开(公告)号：US06180471B2

公开(公告)日：2001-01-30

申请号：US09183062

申请日：1998-10-30

申请人： Peter Chang ,  Gary Hong ,  Joe Ko

发明人： Peter Chang ,  Gary Hong ,  Joe Ko

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L29/7836

摘要： A method of fabricating a high voltage semiconductor device. A semiconductor substrate doped with a first type dopant and comprising a gate is provided. A cap oxide layer is formed on the gate optionally. A first ion implantation with a light second type dopant at a wide angle is performed to form a lightly doped region. A spacer is formed on a side wall of the gate. A second ion implantation with a heavy second type dopant is performed, so that a heavily doped region is formed within the lightly doped region.

摘要翻译： 一种制造高电压半导体器件的方法。 提供掺杂有第一类型掺杂剂并且包括栅极的半导体衬底。 可选地，在栅极上形成帽氧化物层。 进行具有广角的第二种光掺杂剂的第一离子注入以形成轻掺杂区域。 隔板形成在门的侧壁上。 执行具有重的第二类型掺杂剂的第二离子注入，使得在轻掺杂区域内形成重掺杂区域。

公开(公告)号：US06171909B2

公开(公告)日：2001-01-09

申请号：US09293434

申请日：1999-04-16

申请人： Yen-Lin Ding ,  Gary Hong

发明人： Yen-Lin Ding ,  Gary Hong

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method for forming a stacked gate of a flash memory cell is described. A first dielectric layer, a conductive layer and a silicon nitride layer are sequentially formed over a substrate. A photoresist pattern is formed over the silicon nitride layer. The silicon nitride layer, conductive layer, first dielectric layer and substrate are etched by using the photoresist pattern as an etching mask until forming a plurality of trenches in the substrate. An insulating layer is formed over the substrate, wherein the insulating layer has a surface level between a top surface of the conductive layer and a bottom surface of the conductive layer. A conductive spacer is formed on the sidewalls of the conductive layer and silicon nitride layer, wherein the conductive spacer and conductive layer serve as a first gate conductive layer. The silicon nitride layer is removed. A second dielectric layer and a second gate conductive layer are formed over the substrate. The second gate conductive layer, second dielectric layer and first gate conductive layer are patterned to form a control gate, a patterned dielectric layer and a floating gate, respectively.

摘要翻译： 描述了一种用于形成闪存单元的堆叠栅极的方法。 第一电介质层，导电层和氮化硅层依次形成在衬底上。 在氮化硅层上形成光刻胶图形。 通过使用光致抗蚀剂图案作为蚀刻掩模来蚀刻氮化硅层，导电层，第一介电层和衬底，直到在衬底中形成多个沟槽。 在衬底上形成绝缘层，其中绝缘层在导电层的顶表面和导电层的底表面之间具有表面水平。 导电间隔物形成在导电层和氮化硅层的侧壁上，其中导电间隔物和导电层用作第一栅极导电层。 去除氮化硅层。 第二电介质层和第二栅极导电层形成在衬底上。 将第二栅极导电层，第二介电层和第一栅极导电层图案化以分别形成控制栅极，图案化电介质层和浮置栅极。

公开(公告)号：US6150276A

公开(公告)日：2000-11-21

申请号：US313166

申请日：1999-05-17

申请人： Claymens Lee ,  Gary Hong

发明人： Claymens Lee ,  Gary Hong

IPC分类号： H01L21/336 ,  H01L29/49 ,  H01L21/311 ,  H01L21/302

CPC分类号： H01L29/6659 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/6656

摘要： A method for fabricating a metal-oxide semiconductor (MOS) transistor on a semiconductor substrate is described. The invention introduces an air chamber with a low dielectric constant between the gate and the source/drain region so as to lower the fringing electric field between the gate and the source/drain region. Moreover, the dielectric constant of the dielectric layer between the gate and the source/drain region is reduced. Therefore, the gate-to-drain capacitance is decreased in the MOS transistor.

摘要翻译： 描述了在半导体衬底上制造金属氧化物半导体（MOS）晶体管的方法。 本发明在栅极和源极/漏极区域之间引入具有低介电常数的气室，以便降低栅极和源极/漏极区域之间的边缘电场。 此外，栅极和源极/漏极区域之间的介电层的介电常数降低。 因此，MOS晶体管中的栅 - 漏电容减小。