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公开(公告)号：US08588720B2
公开(公告)日：2013-11-19
申请号：US12638822
申请日：2009-12-15
申请人： Gary J. Ballantyne , Jifeng Geng , Bo Sun
发明人： Gary J. Ballantyne , Jifeng Geng , Bo Sun
摘要： Techniques for decimating a first periodic signal to generate a second periodic signal. In an exemplary embodiment, the first periodic signal is divided by a configurable integer ratio divider, and the output of the divider is delayed by a configurable fractional delay. The configurable fractional delay may be noise-shaped using, e.g., sigma-delta modulation techniques to spread the quantization noise of the fractional delay over a wide bandwidth. In an exemplary embodiment, the first and second periodic signals may be used to generate the transmit (TX) and receive (RX) local oscillator (LO) signals for a communications transceiver from a single phase-locked loop (PLL) output.
摘要翻译： 抽取第一周期信号以产生第二周期信号的技术。 在示例性实施例中，第一周期信号由可配置的整数比除法器除以且分频器的输出被延迟可配置的分数延迟。 使用例如Σ-Δ调制技术，可配置分数延迟可以是噪声形状，以在宽带宽上扩展分数延迟的量化噪声。 在示例性实施例中，第一和第二周期信号可以用于从单个锁相环（PLL）输出生成通信收发器的发射（TX）和接收（RX）本地振荡器（LO）信号。
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公开(公告)号：US20110143689A1
公开(公告)日：2011-06-16
申请号：US12638822
申请日：2009-12-15
申请人： Gary J. Ballantyne , Jifeng Geng , Bo Sun
发明人： Gary J. Ballantyne , Jifeng Geng , Bo Sun
摘要： Techniques for decimating a first periodic signal to generate a second periodic signal. In an exemplary embodiment, the first periodic signal is divided by a configurable integer ratio divider, and the output of the divider is delayed by a configurable fractional delay. The configurable fractional delay may be noise-shaped using, e.g., sigma-delta modulation techniques to spread the quantization noise of the fractional delay over a wide bandwidth. In an exemplary embodiment, the first and second periodic signals may be used to generate the transmit (TX) and receive (RX) local oscillator (LO) signals for a communications transceiver from a single phase-locked loop (PLL) output.
摘要翻译： 抽取第一周期信号以产生第二周期信号的技术。 在示例性实施例中，第一周期信号由可配置的整数比除法器除以且分频器的输出被延迟可配置的分数延迟。 使用例如Σ-Δ调制技术，可配置分数延迟可以是噪声形状，以在宽带宽上扩展分数延迟的量化噪声。 在示例性实施例中，第一和第二周期信号可以用于从单个锁相环（PLL）输出生成通信收发器的发射（TX）和接收（RX）本地振荡器（LO）信号。
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3.发明授权公开(公告)号：US08076960B2
公开(公告)日：2011-12-13
申请号：US12432468
申请日：2009-04-29
IPC分类号： H03L7/06
CPC分类号： H03L7/089 , H03C3/0916 , H03C3/0941 , H03C3/095 , H03C3/0966 , H03L7/085
摘要： A digital phase-locked loop (DPLL) supporting two-point modulation is described. In one design, the DPLL includes a phase-to-digital converter and a loop filter operating in a loop, a first processing unit for a lowpass modulation path, and a second processing unit for a highpass modulation path. The first processing unit receives an input modulating signal and provides a first modulating signal to a first point inside the loop after the phase-to-digital converter and prior to the loop filter. The second processing unit receives the input modulating signal and provides a second modulating signal to a second point inside the loop after the loop filter. The first processing unit may include an accumulator that accumulates the input modulating signal to convert frequency to phase. The second processing unit may include a scaling unit that scales the input modulating signal with a variable gain.
摘要翻译： 描述了支持两点调制的数字锁相环（DPLL）。 在一种设计中，DPLL包括一个相位数转换器和一个环路工作的环路滤波器，一个用于低通调制路径的第一处理单元和一个用于高通调制路径的第二处理单元。 第一处理单元接收输入调制信号，并且在相位数转换器之后并且在环路滤波器之前向环路内的第一点提供第一调制信号。 第二处理单元接收输入调制信号，并且在环路滤波器之后向环路内的第二点提供第二调制信号。 第一处理单元可以包括累积输入调制信号以将频率转换为相位的累加器。 第二处理单元可以包括用可变增益来缩放输入调制信号的缩放单元。
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4.发明申请DIGITAL PHASE-LOCKED LOOP WITH TWO-POINT MODULATION USING AN ACCUMULATOR AND A PHASE-TO-DIGITAL CONVERTER 有权使用累加器和相数转换器进行两点调制的数字锁相环公开(公告)号：US20100277211A1
公开(公告)日：2010-11-04
申请号：US12432468
申请日：2009-04-29
IPC分类号： H03L7/06
CPC分类号： H03L7/089 , H03C3/0916 , H03C3/0941 , H03C3/095 , H03C3/0966 , H03L7/085
摘要： A digital phase-locked loop (DPLL) supporting two-point modulation is described. In one design, the DPLL includes a phase-to-digital converter and a loop filter operating in a loop, a first processing unit for a lowpass modulation path, and a second processing unit for a highpass modulation path. The first processing unit receives an input modulating signal and provides a first modulating signal to a first point inside the loop after the phase-to-digital converter and prior to the loop filter. The second processing unit receives the input modulating signal and provides a second modulating signal to a second point inside the loop after the loop filter. The first processing unit may include an accumulator that accumulates the input modulating signal to convert frequency to phase. The second processing unit may include a scaling unit that scales the input modulating signal with a variable gain.
摘要翻译： 描述了支持两点调制的数字锁相环（DPLL）。 在一种设计中，DPLL包括一个相位数转换器和一个环路工作的环路滤波器，一个用于低通调制路径的第一处理单元和一个用于高通调制路径的第二处理单元。 第一处理单元接收输入调制信号，并且在相位数转换器之后并且在环路滤波器之前向环路内的第一点提供第一调制信号。 第二处理单元接收输入调制信号，并且在环路滤波器之后向环路内的第二点提供第二调制信号。 第一处理单元可以包括累积输入调制信号以将频率转换为相位的累加器。 第二处理单元可以包括用可变增益来缩放输入调制信号的缩放单元。
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公开(公告)号：US08098103B2
公开(公告)日：2012-01-17
申请号：US12483927
申请日：2009-06-12
IPC分类号： H03L7/093
CPC分类号： H03L7/093
摘要： Techniques for cancelling a disturbance signal from a PLL output signal. In an aspect, a cancellation signal is combined with the signal input to a VCO or DCO in the PLL. In a further aspect, the appropriate cancellation signal is derived by analyzing one or more signals within the PLL. The signals within the PLL may be correlated against one or more disturbance signal templates, such as a sinusoid having a known frequency, to derive one or more correlation coefficients. The coefficients may be applied to weight one or more disturbance synthesis functions to generate the cancellation signal. Further aspects provide for joint analysis, synthesis, and cancellation of signals having unknown frequency from the PLL output.
摘要翻译： 从PLL输出信号中消除干扰信号的技术。 在一方面，消除信号与输入到PLL中的VCO或DCO的信号组合。 在另一方面，通过分析PLL内的一个或多个信号来导出适当的抵消信号。 PLL内的信号可以与一个或多个干扰信号模板（例如具有已知频率的正弦波）相关，以导出一个或多个相关系数。 可以应用系数来加权一个或多个干扰合成功能以产生消除信号。 其他方面提供了从PLL输出端对未知频率的信号的联合分析，合成和消除。
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公开(公告)号：US20100315169A1
公开(公告)日：2010-12-16
申请号：US12483927
申请日：2009-06-12
IPC分类号： H03L7/097
CPC分类号： H03L7/093
摘要： Techniques for cancelling a disturbance signal from a PLL output signal. In an aspect, a cancellation signal is combined with the signal input to a VCO or DCO in the PLL. In a further aspect, the appropriate cancellation signal is derived by analyzing one or more signals within the PLL. The signals within the PLL may be correlated against one or more disturbance signal templates, such as a sinusoid having a known frequency, to derive one or more correlation coefficients. The coefficients may be applied to weight one or more disturbance synthesis functions to generate the cancellation signal. Further aspects provide for joint analysis, synthesis, and cancellation of signals having unknown frequency from the PLL output.
摘要翻译： 从PLL输出信号中消除干扰信号的技术。 在一方面，消除信号与输入到PLL中的VCO或DCO的信号组合。 在另一方面，通过分析PLL内的一个或多个信号来导出适当的抵消信号。 PLL内的信号可以与一个或多个干扰信号模板（例如具有已知频率的正弦波）相关，以导出一个或多个相关系数。 可以应用系数来加权一个或多个干扰合成功能以产生消除信号。 其他方面提供了从PLL输出端对未知频率的信号的联合分析，合成和消除。
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公开(公告)号：US08446191B2
公开(公告)日：2013-05-21
申请号：US12632053
申请日：2009-12-07
IPC分类号： H03L7/06
摘要： A phase locked loop (PLL) device includes a digital differentiator configured to differentiate a digital loop signal to at least partially compensate for the integration of an analog current signal by an analog integrator. A digital to analog converter (DAC) includes a current source output stage that generates the analog current signal based on an digital input signal. The analog integrator integrates the analog current signal to generate a voltage control signal for controlling a voltage controlled oscillator (VCO).
摘要翻译： 锁相环（PLL）装置包括数字微分器，其被配置为区分数字环路信号以至少部分地补偿模拟积分器对模拟电流信号的积分。 数模转换器（DAC）包括基于数字输入信号产生模拟电流信号的电流源输出级。 模拟积分器对模拟电流信号进行积分，以产生用于控制压控振荡器（VCO）的电压控制信号。
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公开(公告)号：US08254855B2
公开(公告)日：2012-08-28
申请号：US12116539
申请日：2008-05-07
CPC分类号： H04B1/1036 , H04B1/7107
摘要： Techniques for identifying and suppressing frequency spurs in a signal are disclosed. In an embodiment, an incoming signal is rotated by a frequency related to a spur frequency, and an estimate of the content of the rotated signal is derived. The estimate may be subtracted from the rotated incoming signal, and the result de-rotated by the spur frequency. In an embodiment, the incoming signal may be rotated such that the spur is centered at DC. In an alternative embodiment, the estimate may be de-rotated before being subtracted from the original incoming signal. Techniques for addressing multiple spurs using serial and parallel architectures are disclosed. Further disclosed are techniques for searching for the presence of spurs in an incoming signal, and tracking spur frequencies over time.
摘要翻译： 公开了用于识别和抑制信号中的频率杂散的技术。 在一个实施例中，输入信号被旋转与杂波频率相关的频率，并且导出旋转信号的内容的估计。 可以从旋转的输入信号中减去估计值，并且结果由杂散频率去旋转。 在一个实施例中，输入信号可以旋转，使得支线以DC为中心。 在替代实施例中，估计可以在从原始输入信号中减去之前被去转动。 公开了使用串行和并行架构寻址多个杂散的技术。 进一步公开的是用于在输入信号中搜索马刺的存在的技术，以及随时间跟踪刺激频率。
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公开(公告)号：US20100310031A1
公开(公告)日：2010-12-09
申请号：US12478506
申请日：2009-06-04
IPC分类号： H03D3/24
CPC分类号： H03L7/08 , H03C3/0941 , H03C3/095 , H03C3/0966 , H03L2207/50
摘要： A Digital Phase-Locked Loop (DPLL) involves a Time-to-Digital Converter (TDC) that receives a DCO output signal and a reference clock and outputs a first stream of digital values. Quantization noise is reduced by clocking the TDC at a high rate. Downsampling circuitry converts the first stream into a second stream. The second stream is supplied to a phase detecting summer of the DPLL such that a control portion of the DPLL can switch at a lower rate to reduce power consumption. The DPLL is therefore referred to as a multi-rate DPLL. A third stream of digital tuning words output by the control portion is upsampled before being supplied to the DCO so that the DCO can be clocked at the higher rate, thereby reducing digital images. In a receiver application, no upsampling is performed and the DCO is clocked at the lower rate, thereby further reducing power consumption.
摘要翻译： 数字锁相环（DPLL）涉及一个时间数字转换器（TDC），它接收DCO输出信号和参考时钟并输出第一个数字值。 通过以较高的速率计时TDC来减少量化噪声。 下采样电路将第一流转换为第二流。 第二流被提供给DPLL的相位检测加法器，使得DPLL的控制部分可以以较低的速率切换以降低功耗。 因此，DPLL被称为多速率DPLL。 由控制部分输出的第三个数字调谐字流在被提供给DCO之前被上采样，从而可以以更高的速率计时DCO，从而减少数字图像。 在接收机应用中，不执行上采样，并且以较低的速率对DCO进行计时，从而进一步降低功耗。
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公开(公告)号：US07974807B2
公开(公告)日：2011-07-05
申请号：US12233400
申请日：2008-09-18
IPC分类号： G06F19/00
CPC分类号： H03L7/091 , H03L2207/50
摘要： Techniques for adaptively calibrating a TDC output signal in a digital phase-locked loop (DPLL). In an exemplary embodiment, a calibration factor multiplied to the TDC output signal is adaptively adjusted to minimize a magnitude function of a phase comparator output signal of the DPLL. In an exemplary embodiment, the calibration factor may be adjusted using an exemplary embodiment of the least-mean squares (LMS) algorithm. Further techniques for simplifying the adaptive algorithm for hardware implementation are described.
摘要翻译： 用于在数字锁相环（DPLL）中自适应校准TDC输出信号的技术。 在示例性实施例中，自适应地调整与TDC输出信号相乘的校准因子以最小化DPLL的相位比较器输出信号的幅度函数。 在示例性实施例中，可以使用最小均方（LMS）算法的示例性实施例来调整校准因子。 描述了用于简化用于硬件实现的自适应算法的进一步的技术。
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