公开(公告)号：US20060104298A1

公开(公告)日：2006-05-18

申请号：US11114641

申请日：2005-04-25

申请人： Gary McAlpine ,  Tanmay Gupta ,  Manoj Wadekar

发明人： Gary McAlpine ,  Tanmay Gupta ,  Manoj Wadekar

IPC分类号： H04L1/00

CPC分类号： H04L47/10 ,  H04L47/115 ,  H04L47/263 ,  H04L49/90 ,  H04L49/9078

摘要： A source node receives related frames of data to be transmitted from the source node to a destination node and places the frames in a queue. The queue is associated with a communication path over which the related frames are to be transmitted to the destination node. An interface that couples the source node to the communication path receives an indication directed to the source node of traffic congestion in the communication path. In response, the source node controls the rate at which the related frames of data are transferred from the queue to a transmit buffer accessible to the interface, in order to relieve the traffic congestion in the communication path.

摘要翻译： 源节点接收要从源节点发送到目的节点的相关数据帧，并将帧放入队列。 队列与通信路径相关联，通过该路径将相关帧发送到目的地节点。 将源节点耦合到通信路径的接口接收到通信路径中针对源节点的业务拥塞的指示。 作为响应，源节点控制相关数据帧从队列传送到接口可访问的发送缓冲器的速率，以便减轻通信路径中的业务拥塞。

公开(公告)号：US20070058532A1

公开(公告)日：2007-03-15

申请号：US11227897

申请日：2005-09-15

申请人： Manoj Wadekar ,  Gary McAlpine ,  Tanmay Gupta

发明人： Manoj Wadekar ,  Gary McAlpine ,  Tanmay Gupta

IPC分类号： H04L12/26

CPC分类号： H04L47/26 ,  H04L43/16 ,  H04L47/11 ,  H04L47/33

摘要： According to one embodiment of the invention, a method comprises measuring traffic congestion experienced by a message transmitted from a source device, and if the measured traffic congestion exceeds a threshold limit, altering at least one bit within a Layer 2 (L2) header of the message. This bit alteration is subsequently used to determine when to notify a source of the message that the message experienced traffic congestion.

摘要翻译： 根据本发明的一个实施例，一种方法包括测量从源设备发送的消息所经历的业务拥塞，并且如果所测量的业务拥塞超过阈值限制，则改变所述第二层（L2）报头中的至少一个比特 信息。 该位改变随后被用于确定何时通知消息的消息，消息经历交通拥堵。

公开(公告)号：US6011798A

公开(公告)日：2000-01-04

申请号：US912260

申请日：1997-08-15

申请人： Gary McAlpine

发明人： Gary McAlpine

IPC分类号： H04L12/56 ,  H04Q11/04 ,  H04L12/28

CPC分类号： H04L12/5601 ,  H04L2012/5651 ,  H04L2012/5679

摘要： An adaptive rate control scheduler multiplexes virtual circuit data stream elements for transmission onto a network from a network node. The rate control scheduler is an adaptive circuit that utilizes a schedule table (having multiple time windows) and a set of virtual circuit (VC) specific rate control parameters to supply a transmit controller with a stream of tokens (each of which represents an active VC). The order in which tokens are supplied to the transmit controller is based upon their respective time slot locations in the schedule table. Each time a token is processed by the transmit scheduler, a target time for the next processing of the VC represented by the token is calculated, based upon the stored VC-specific parameters. The token is then inserted into the schedule table in the nearest available time slot to the calculated target time. Included in the calculation of the next target time for a particular token is a gain function based upon an accumulated error value for the associated VC. The accumulated error represents error introduced into the VC's data stream by the scheduling process.

摘要翻译： 自适应速率控制调度器从网络节点复用用于传输到网络的虚拟电路数据流元件。 速率控制调度器是利用调度表（具有多个时间窗口）和一组虚拟电路（VC）特定速率控制参数的自适应电路，以向发送控制器提供令牌流（每个代表活动VC ）。 将令牌提供给发送控制器的顺序基于其在调度表中的相应时隙位置。 每次由发送调度器处理令牌时，基于存储的VC特定参数来计算用于由令牌表示的VC的下一个处理的目标时间。 然后将令牌插入到计划目标时间的最近可用时隙中的计划表中。 在特定令牌的下一个目标时间的计算中包括基于相关VC的累积误差值的增益函数。 累积误差表示通过调度过程引入VC数据流的错误。

公开(公告)号：US20060053117A1

公开(公告)日：2006-03-09

申请号：US10957895

申请日：2004-09-30

申请人： Gary McAlpine ,  Tanmay Gupta ,  Manoj Wadekar

发明人： Gary McAlpine ,  Tanmay Gupta ,  Manoj Wadekar

IPC分类号： G06F17/30

CPC分类号： H04L47/20 ,  H04L47/10 ,  H04L47/125 ,  H04L47/2441 ,  H04L47/26 ,  H04L47/30 ,  H04L47/6215

摘要： A node uses a two dimensional array of transmit queues to store frames to be transmitted from the node to another node. The size of the array is governed by the number of directions to which the other node may forward frames once received from the node, and the number of priorities that may be associated with the frames. The transmit queues are distinguished from each other based on direction and priority. A transmitter transmits frames dequeued from the transmit queues to the other node. Control logic that controls the transmit queues receives an indication from the other node whether the other node is experiencing traffic congestion in any of the directions and the priority of frames at or below which the control logic is to control the dequeuing of frames from transmit queues corresponding to the directions in which the other node is experiencing traffic congestion.

摘要翻译： 节点使用发射队列的二维阵列来存储要从节点发送到另一个节点的帧。 阵列的大小由另一个节点可以一旦从节点接收到的帧转发的方向的数量以及可能与帧相关联的优先级的数量来控制。 基于方向和优先级将发送队列彼此区分开。 发射机将发送队列出队的帧发送到另一个节点。 控制发送队列的控制逻辑从另一个节点接收指示，否则其他节点正在任何方向上经历业务拥塞，以及控制逻辑要控制从对应于发送队列的帧出队的帧的优先级 到另一个节点遇到交通拥堵的方向。

公开(公告)号：US20050144422A1

公开(公告)日：2005-06-30

申请号：US10750567

申请日：2003-12-30

申请人： Gary McAlpine ,  Dave Minturn ,  Greg Regnier ,  Frank Berry

发明人： Gary McAlpine ,  Dave Minturn ,  Greg Regnier ,  Frank Berry

IPC分类号： G06F12/02 ,  G06F12/10 ,  G06F12/14 ,  G06F12/08

CPC分类号： G06F12/1081 ,  G06F12/1036 ,  G06F12/109 ,  G06F12/1458

摘要： A virtual to physical address translator in which a requesting process supplements a virtual memory address with a shortcut to a physical address associated with one level of a multi-level virtual address translation table. A second process, such as an I/O process, receives the shortcut and the virtual address and uses an address translator to determine the physical address. In some implementations, the shortcut may be made opaque to the requesting process such that the requesting process cannot determine the physical address represented in the shortcut.

摘要翻译： 一种虚拟到物理地址转换器，其中请求过程利用与多级虚拟地址转换表的一个级别相关联的物理地址的快捷方式来补充虚拟存储器地址。 诸如I / O进程的第二进程接收快捷方式和虚拟地址，并使用地址转换器来确定物理地址。 在一些实施方案中，快捷方式可以对请求过程变得不透明，使得请求进程不能确定快捷方式中表示的物理地址。

公开(公告)号：US07457245B2

公开(公告)日：2008-11-25

申请号：US10957895

申请日：2004-09-30

申请人： Gary McAlpine ,  Tanmay Gupta ,  Manoj K. Wadekar

发明人： Gary McAlpine ,  Tanmay Gupta ,  Manoj K. Wadekar

IPC分类号： H04J1/16

CPC分类号： H04L47/20 ,  H04L47/10 ,  H04L47/125 ,  H04L47/2441 ,  H04L47/26 ,  H04L47/30 ,  H04L47/6215

摘要： A node uses a two dimensional array of transmit queues to store frames to be transmitted from the node to another node. The size of the array is governed by the number of directions to which the other node may forward frames once received from the node, and the number of priorities that may be associated with the frames. The transmit queues are distinguished from each other based on direction and priority. A transmitter transmits frames dequeued from the transmit queues to the other node. Control logic that controls the transmit queues receives an indication from the other node whether the other node is experiencing traffic congestion in any of the directions and the priority of frames at or below which the control logic is to control the dequeuing of frames from transmit queues corresponding to the directions in which the other node is experiencing traffic congestion.

摘要翻译： 节点使用发射队列的二维阵列来存储要从节点发送到另一个节点的帧。 阵列的大小由另一个节点可以一旦从节点接收到的帧转发的方向的数量以及可能与帧相关联的优先级的数量来控制。 基于方向和优先级将发送队列彼此区分开。 发射机将发送队列出队的帧发送到另一个节点。 控制发送队列的控制逻辑从另一个节点接收指示，否则其他节点正在任何方向上经历业务拥塞，以及控制逻辑要控制从对应于发送队列的帧出队的帧的优先级 到另一个节点遇到交通拥堵的方向。

公开(公告)号：US20060072563A1

公开(公告)日：2006-04-06

申请号：US10959488

申请日：2004-10-05

申请人： Greg Regnier ,  Vikram Saletore ,  Gary McAlpine ,  Ram Huggahalli ,  Ravishankar Iyer ,  Ramesh Illikkal ,  David Minturn ,  Donald Newell ,  Srihari Makineni

发明人： Greg Regnier ,  Vikram Saletore ,  Gary McAlpine ,  Ram Huggahalli ,  Ravishankar Iyer ,  Ramesh Illikkal ,  David Minturn ,  Donald Newell ,  Srihari Makineni

IPC分类号： H04L12/56

CPC分类号： H04L49/9094 ,  H04L49/90 ,  H04L49/9042 ,  H04L49/9063

摘要： In general, the disclosure describes a variety of techniques that can enhance packet processing operations.

摘要翻译： 通常，本公开描述了可以增强分组处理操作的各种技术。

公开(公告)号：US20050138622A1

公开(公告)日：2005-06-23

申请号：US10740771

申请日：2003-12-18

申请人： Gary McAlpine ,  Dave Minturn

发明人： Gary McAlpine ,  Dave Minturn

IPC分类号： G06F9/38 ,  G06F9/46 ,  G06F9/48

CPC分类号： G06F9/485 ,  G06F9/3851

摘要： A method and apparatus for handling multiple processing streams in parallel on a single thread of a processing device. In one embodiment, a parallel processing agent includes a scheduler that multiplexes a number of processing streams, or pipelines, on a single thread of execution.

摘要翻译： 一种在处理设备的单个线程上并行处理多个处理流的方法和装置。 在一个实施例中，并行处理代理包括在单个执行线程上复用多个处理流或管线的调度器。

公开(公告)号：US4837785A

公开(公告)日：1989-06-06

申请号：US504150

申请日：1983-06-14

申请人： Gary McAlpine

发明人： Gary McAlpine

IPC分类号： G06F13/38 ,  G06F13/364 ,  G06F13/42

CPC分类号： G06F13/364 ,  G06F13/4291

摘要： A data transfer system with improved data transfer efficiency is provided. The system consists of a data interchange bus having two data transfer signal paths, an address signal path, and a plurality of control signal paths. Data interchange adapters and memory interchange adapters are coupled to the bus for transferring data thereover. A data interchange adapter transfers data on the first data signal path to another data interchange adapter or to a memory interchange adapter for storage in a memory device. A memory interchange adapter transfers data obtained from a memory device on the second data signal path to a data interchange adapter. Data transfers on the two data signal paths may be made simultaneously. Data transfers on both data signal paths are made synchronously. When an interchange adapter has data to be transferred, it provides an access request signal to a data interchange bus controller which intermittently latches all outstanding access requests, examines them, and produces a sequence of grant signals, each satisfying one of the latched request signals. When the sequence is completed, the controller again latches the access requests which had been raised during the prior latching and granting procedure. The data interchange adapter is further provided with the capability of coupling to two other data buses while coupled to the data interchange bus and includes interface and control circuitry for routing signals between any two of the three buses.

摘要翻译： 提供了具有改进的数据传输效率的数据传输系统。 该系统由具有两个数据传输信号路径，地址信号路径和多个控制信号路径的数据交换总线组成。 数据交换适配器和存储器交换适配器耦合到总线，用于在其上传输数据。 数据交换适配器将第一数据信号路径上的数据传送到另一个数据交换适配器或存储器交换适配器，以存储在存储设备中。 存储器交换适配器将从第二数据信号路径上的存储器件获得的数据传送到数据交换适配器。 两个数据信号路径上的数据传输可以同时进行。 两个数据信号路径上的数据传输是同步进行的。 当交换适配器具有要传送的数据时，它向数据交换总线控制器提供访问请求信号，该数据交换总线控制器间歇地锁存所有未完成的访问请求，检查它们，并且产生一系列授权信号，每个请求信号满足锁存的请求信号之一。 当序列完成时，控制器再次锁存在先前锁存和授权过程中已经提出的访问请求。 数据交换适配器还具有耦合到两个数据总线同时耦合到数据交换总线的能力，并且包括用于在三个总线中的任何两个之间路由信号的接口和控制电路。

公开(公告)号：US07733770B2

公开(公告)日：2010-06-08

申请号：US11114641

申请日：2005-04-25

申请人： Gary McAlpine ,  Tanmay Gupta ,  Manoj Wadekar

发明人： Gary McAlpine ,  Tanmay Gupta ,  Manoj Wadekar

IPC分类号： G01R31/08 ,  H04B3/20 ,  H04L12/50 ,  H04L12/28

CPC分类号： H04L47/10 ,  H04L47/115 ,  H04L47/263 ,  H04L49/90 ,  H04L49/9078

摘要： A source node receives related frames of data to be transmitted from the source node to a destination node and places the frames in a queue. The queue is associated with a communication path over which the related frames are to be transmitted to the destination node. An interface that couples the source node to the communication path receives an indication directed to the source node of traffic congestion in the communication path. In response, the source node controls the rate at which the related frames of data are transferred from the queue to a transmit buffer accessible to the interface, in order to relieve the traffic congestion in the communication path.

摘要翻译： 源节点接收要从源节点发送到目的节点的相关数据帧，并将帧放入队列。 队列与通信路径相关联，通过该路径将相关帧发送到目的地节点。 将源节点耦合到通信路径的接口接收到通信路径中针对源节点的业务拥塞的指示。 作为响应，源节点控制相关数据帧从队列传送到接口可访问的发送缓冲器的速率，以便减轻通信路径中的业务拥塞。