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    Method and apparatus for managing buffers in PCI bridges
    1.
    发明授权
    Method and apparatus for managing buffers in PCI bridges 有权
    用于管理PCI桥中缓冲区的方法和装置

    公开(公告)号：US07213094B2

    公开(公告)日：2007-05-01

    申请号：US10780372

    申请日：2004-02-17

    申请人： Geetani R. Edirisooriya ,  Aniruddha P. Joshi ,  John P. Lee

    发明人： Geetani R. Edirisooriya ,  Aniruddha P. Joshi ,  John P. Lee

    IPC分类号： G06F13/36

    CPC分类号： G06F13/4027

    摘要： Method and apparatus for supporting multi-function PCI devices in PCI bridges. Respective pre-fetch buffers are allocated in response to respective initial data transfer requests issued by a multi-function PCI device. A programmable buffer fill watermark is set up for each pre-fetch buffer. While a portion of data corresponding to the data transfer requests fill the pre-fetch buffers, the fill level of each buffer is monitored to determine if it meets or exceeds its buffer fill watermark. In response to such a condition, the multi-function PCI device is connected to the PCI bridge and a virtual buffer is mapped to the pre-fetch buffer. The pre-fetch buffer is then emptied. During subsequent data transfers, each of the pre-fetch buffer becomes filled, the PCI device is connected, and the virtual buffer is mapped to the filled buffer. The process is continued until all data corresponding to the original data transfer request is received by the multi-function PCI device.

    摘要翻译： 支持PCI桥中多功能PCI设备的方法和装置。 响应于由多功能PCI设备发出的各自的初始数据传送请求分配各自的预取缓冲器。 为每个预取缓冲区设置可编程缓冲区填充水印。 虽然对应于数据传输请求的一部分数据填充预取缓冲器，但是监视每个缓冲器的填充级别以确定其是否满足或超过其缓冲区填充水印。 响应于这种情况，多功能PCI设备连接到PCI桥，虚拟缓冲器被映射到预取缓冲器。 然后将预取缓冲区清空。 在随后的数据传输期间，每个预取缓冲区都被填满，PCI设备被连接，虚拟缓冲区被映射到已填充的缓冲区。 该过程一直持续到多功能PCI设备接收到与原始数据传送请求相对应的所有数据。

    Apparatus and method for maintaining data integrity following parity error detection
    2.
    发明授权
    Apparatus and method for maintaining data integrity following parity error detection 有权
    用于在奇偶校验错误检测之后维持数据完整性的装置和方法

    公开(公告)号：US07251755B2

    公开(公告)日：2007-07-31

    申请号：US10779140

    申请日：2004-02-13

    申请人： Aniruddha P. Joshi ,  John P. Lee ,  Geetani R. Edirisooriya

    发明人： Aniruddha P. Joshi ,  John P. Lee ,  Geetani R. Edirisooriya

    IPC分类号： G06F11/00

    CPC分类号： G06F11/0793 ,  G06F11/0745 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/079

    摘要： In some embodiments, a method and apparatus for maintaining data integrity following parity error detection are described. In one embodiment, the method includes the blockage of bus transactions in response to detection of a parity error. Once bus transactions are suspended, a parity error handler routine is invoked to perform parity error recovery according to stored transaction information regarding an error bus transaction of the detected parity error. In one embodiment, the stored information includes a bus master that caused the error, as well as an address associated with the corrupt data for which the parity error was asserted. In one embodiment, data logging is performed to track the bus masters associated with error bus transactions to enable identification of problematic or old hardware devices. Other embodiments are described and claims.

    摘要翻译： 在一些实施例中，描述了用于在奇偶校验错误检测之后维持数据完整性的方法和装置。 在一个实施例中，该方法包括响应于奇偶校验错误的检测而阻塞总线事务。 一旦暂停总线事务，根据存储的关于检测到的奇偶校验错误的错误总线事务的事务信息，调用奇偶校验错误处理程序来执行奇偶校验错误恢复。 在一个实施例中，所存储的信息包括导致错误的总线主机，以及与被断言奇偶校验错误的损坏数据相关联的地址。 在一个实施例中，执行数据记录以跟踪与错误总线事务相关联的总线主控器，以便能够识别有问题的或旧的硬件设备。 其他实施例被描述和权利要求。

    Method, system, and apparatus to decrease CPU temperature through I/O bus throttling
    3.
    发明授权
    Method, system, and apparatus to decrease CPU temperature through I/O bus throttling 有权
    通过I / O总线调节降低CPU温度的方法，系统和设备

    公开(公告)号：US07596638B2

    公开(公告)日：2009-09-29

    申请号：US10873779

    申请日：2004-06-21

    申请人： John P. Lee ,  Aniruddha P. Joshi ,  Geetani R. Edirisooriya

    发明人： John P. Lee ,  Aniruddha P. Joshi ,  Geetani R. Edirisooriya

    IPC分类号： G06F3/00

    CPC分类号： G06F1/324 ,  G06F1/206 ,  G06F1/3209 ,  Y02D10/126

    摘要： A method, apparatus, and system are disclosed. In one embodiment the method detects a temperature event in a processor and then modifies the bus frequency of an I/O bus coupled to an I/O controller hub in response to the temperature event. In another embodiment, the apparatus includes a temperature detection unit that detects a temperature event in a processor and, additionally, a bus frequency modification unit that will modify the bus frequency of an I/O bus in response to the temperature event.

    摘要翻译： 公开了一种方法，装置和系统。 在一个实施例中，该方法检测处理器中的温度事件，然后响应于温度事件修改耦合到I / O控制器集线器的I / O总线的总线频率。 在另一个实施例中，该装置包括温度检测单元，其检测处理器中的温度事件，另外还包括总线频率修改单元，其将响应于温度事件修改I / O总线的总线频率。