公开(公告)号：US07596638B2

公开(公告)日：2009-09-29

申请号：US10873779

申请日：2004-06-21

申请人： John P. Lee ,  Aniruddha P. Joshi ,  Geetani R. Edirisooriya

发明人： John P. Lee ,  Aniruddha P. Joshi ,  Geetani R. Edirisooriya

IPC分类号： G06F3/00

CPC分类号： G06F1/324 ,  G06F1/206 ,  G06F1/3209 ,  Y02D10/126

摘要： A method, apparatus, and system are disclosed. In one embodiment the method detects a temperature event in a processor and then modifies the bus frequency of an I/O bus coupled to an I/O controller hub in response to the temperature event. In another embodiment, the apparatus includes a temperature detection unit that detects a temperature event in a processor and, additionally, a bus frequency modification unit that will modify the bus frequency of an I/O bus in response to the temperature event.

摘要翻译： 公开了一种方法，装置和系统。 在一个实施例中，该方法检测处理器中的温度事件，然后响应于温度事件修改耦合到I / O控制器集线器的I / O总线的总线频率。 在另一个实施例中，该装置包括温度检测单元，其检测处理器中的温度事件，另外还包括总线频率修改单元，其将响应于温度事件修改I / O总线的总线频率。

公开(公告)号：US07251755B2

公开(公告)日：2007-07-31

申请号：US10779140

申请日：2004-02-13

申请人： Aniruddha P. Joshi ,  John P. Lee ,  Geetani R. Edirisooriya

发明人： Aniruddha P. Joshi ,  John P. Lee ,  Geetani R. Edirisooriya

IPC分类号： G06F11/00

CPC分类号： G06F11/0793 ,  G06F11/0745 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/079

摘要： In some embodiments, a method and apparatus for maintaining data integrity following parity error detection are described. In one embodiment, the method includes the blockage of bus transactions in response to detection of a parity error. Once bus transactions are suspended, a parity error handler routine is invoked to perform parity error recovery according to stored transaction information regarding an error bus transaction of the detected parity error. In one embodiment, the stored information includes a bus master that caused the error, as well as an address associated with the corrupt data for which the parity error was asserted. In one embodiment, data logging is performed to track the bus masters associated with error bus transactions to enable identification of problematic or old hardware devices. Other embodiments are described and claims.

摘要翻译： 在一些实施例中，描述了用于在奇偶校验错误检测之后维持数据完整性的方法和装置。 在一个实施例中，该方法包括响应于奇偶校验错误的检测而阻塞总线事务。 一旦暂停总线事务，根据存储的关于检测到的奇偶校验错误的错误总线事务的事务信息，调用奇偶校验错误处理程序来执行奇偶校验错误恢复。 在一个实施例中，所存储的信息包括导致错误的总线主机，以及与被断言奇偶校验错误的损坏数据相关联的地址。 在一个实施例中，执行数据记录以跟踪与错误总线事务相关联的总线主控器，以便能够识别有问题的或旧的硬件设备。 其他实施例被描述和权利要求。

公开(公告)号：US07213094B2

公开(公告)日：2007-05-01

申请号：US10780372

申请日：2004-02-17

申请人： Geetani R. Edirisooriya ,  Aniruddha P. Joshi ,  John P. Lee

发明人： Geetani R. Edirisooriya ,  Aniruddha P. Joshi ,  John P. Lee

IPC分类号： G06F13/36

CPC分类号： G06F13/4027

摘要： Method and apparatus for supporting multi-function PCI devices in PCI bridges. Respective pre-fetch buffers are allocated in response to respective initial data transfer requests issued by a multi-function PCI device. A programmable buffer fill watermark is set up for each pre-fetch buffer. While a portion of data corresponding to the data transfer requests fill the pre-fetch buffers, the fill level of each buffer is monitored to determine if it meets or exceeds its buffer fill watermark. In response to such a condition, the multi-function PCI device is connected to the PCI bridge and a virtual buffer is mapped to the pre-fetch buffer. The pre-fetch buffer is then emptied. During subsequent data transfers, each of the pre-fetch buffer becomes filled, the PCI device is connected, and the virtual buffer is mapped to the filled buffer. The process is continued until all data corresponding to the original data transfer request is received by the multi-function PCI device.

摘要翻译： 支持PCI桥中多功能PCI设备的方法和装置。 响应于由多功能PCI设备发出的各自的初始数据传送请求分配各自的预取缓冲器。 为每个预取缓冲区设置可编程缓冲区填充水印。 虽然对应于数据传输请求的一部分数据填充预取缓冲器，但是监视每个缓冲器的填充级别以确定其是否满足或超过其缓冲区填充水印。 响应于这种情况，多功能PCI设备连接到PCI桥，虚拟缓冲器被映射到预取缓冲器。 然后将预取缓冲区清空。 在随后的数据传输期间，每个预取缓冲区都被填满，PCI设备被连接，虚拟缓冲区被映射到已填充的缓冲区。 该过程一直持续到多功能PCI设备接收到与原始数据传送请求相对应的所有数据。

公开(公告)号：US07376782B2

公开(公告)日：2008-05-20

申请号：US11172254

申请日：2005-06-29

申请人： Jasper Balraj ,  Geetani R. Edirisooriya ,  John P. Lee ,  Robert Strong ,  Jeffrey L. Rabe ,  Amber Huffman ,  Daniel Nemiroff ,  Rajeev Nalawadi

发明人： Jasper Balraj ,  Geetani R. Edirisooriya ,  John P. Lee ,  Robert Strong ,  Jeffrey L. Rabe ,  Amber Huffman ,  Daniel Nemiroff ,  Rajeev Nalawadi

IPC分类号： G06F12/00

CPC分类号： G06F9/4401

摘要： A computer system provides a program access to a first register during real mode operation by using an index register and a data register, wherein the index register and the data register are located in real mode memory space and the first register is located outside of real mode memory space.

摘要翻译： 计算机系统通过使用索引寄存器和数据寄存器在实模式操作期间提供对第一寄存器的访问，其中索引寄存器和数据寄存器位于实模式存储器空间中，并且第一寄存器位于实模式之外 内存空间。

公开(公告)号：US06973526B2

公开(公告)日：2005-12-06

申请号：US10183641

申请日：2002-06-28

申请人： John P. Lee ,  Atul Kwatra ,  Aniruddha P. Joshi

发明人： John P. Lee ,  Atul Kwatra ,  Aniruddha P. Joshi

IPC分类号： G06F13/14 ,  G06F13/40

CPC分类号： G06F13/4004 ,  G06F2213/0024

摘要： Access to internal configuration registers on a computer system's chipset using an external micro-controller is provided. A SMB configuration read command including a register address may be received from an external micro-controller. Access to an internal bus may be requested from a bus arbiter. If internal bus access is granted, the SMB configuration read command may be forwarded to a device including the identified register address using the internal bus. In response to the SMB configuration read command, configuration register values from the device may be received. The configuration register values may be forwarded to the external micro-controller.

摘要翻译： 提供使用外部微控制器访问计算机系统芯片组上的内部配置寄存器。 可以从外部微控制器接收包括寄存器地址的SMB配置读取命令。 可以从总线仲裁器请求访问内部总线。 如果内部总线访问被授予，SMB配置读取命令可以使用内部总线转发到包括所识别的寄存器地址的设备。 响应于SMB配置读命令，可以接收来自设备的配置寄存器值。 配置寄存器值可以转发到外部微控制器。

公开(公告)号：US07103692B2

公开(公告)日：2006-09-05

申请号：US10295543

申请日：2002-11-14

申请人： Atul Kwatra ,  John P. Lee ,  Aniruddha P. Joshi ,  Thomas M. Slaight ,  Peter R. Munguia

发明人： Atul Kwatra ,  John P. Lee ,  Aniruddha P. Joshi ,  Thomas M. Slaight ,  Peter R. Munguia

IPC分类号： G06F13/00 ,  G06F3/00

CPC分类号： G06F13/24

摘要： Embodiments of the present invention provide a method and apparatus to allow an I/O controller to alert an external controller using an enhanced SMBus implementation that enables bi-directional capability on SMBALERT#. I/O controller includes an auxiliary control register and alert output enable (AOEN) register. When host sets AOE bit in auxiliary control register, SMBALERT# signal is configured as an output signal with bi-directional functionality. External controller uses an interface command to write to AOEN register and determine events/conditions it wants to be alerted on. SMBALERT# is activated in response to a detected event/condition. In response to SMBALERT#, external controller determines the alert generation condition using byte read commands on the system management bus, and clears SMBALERT#.

摘要翻译： 本发明的实施例提供一种允许I / O控制器使用能够在SMBALERT＃上实现双向能力的增强型SMBus实现来向外部控制器发出警报的方法和装置。 I / O控制器包括辅助控制寄存器和报警输出使能（AOEN）寄存器。 当主机在辅助控制寄存器中设置AOE位时，SMBALERT＃信号被配置为具有双向功能的输出信号。 外部控制器使用接口命令写入AOEN寄存器，并确定要发送的事件/条件。 响应于检测到的事件/条件，SMBALERT＃被激活。 响应SMBALERT＃，外部控制器使用系统管理总线上的字节读取命令确定警报生成条件，并清除SMBALERT＃。

公开(公告)号：US5285765A

公开(公告)日：1994-02-15

申请号：US995840

申请日：1992-12-23

申请人： John P. Lee

发明人： John P. Lee

IPC分类号： F41B11/02 ,  F41B11/00

CPC分类号： F41B11/52

摘要： A gas-powered paint ball gun in which a magazine is attached tangentially to a firing chamber or barrel. An opening is provided in the magazine so as to release back-pressure. Paint balls are fed into the firing chamber through the magazine in a direction tangent to the firing chamber and in a direction perpendicular to the radial direction of the firing chamber or barrel. The paint balls being loaded into the firing chamber each have a limited radial distance to travel and therefore have a limited travel period. The unique configuration enables each paint ball being loaded into the chamber to come to rest in the firing chamber more rapidly and thereby reduces the risk of the gun becoming jammed. Further, this configuration enables the gun to be fired more rapidly and with greater assurance that the gun will not jam.

摘要翻译： 一种气动油漆球枪，其中刀库与燃烧室或枪管切向相连。 在该盒中设置开口以释放背压。 油漆球通过刀库沿着与燃烧室相切的方向并且在垂直于燃烧室或枪管的径向的方向上被送入燃烧室。 装载到射出室中的涂料球各自具有有限的径向行进距离，因此具有有限的行进周期。 独特的配置使得每个油漆球装载到室中能够更快地停留在燃烧室中，从而降低了枪被卡住的风险。 此外，这种配置使枪能够更快地被射击并且更确保枪不会卡住。

公开(公告)号：US20140108695A1

公开(公告)日：2014-04-17

申请号：US14141574

申请日：2013-12-27

申请人： Ramana Rachakonda ,  Lance E. Hacking ,  Mahesh K. Reddy ,  Lori R. Borger ,  Chee Hak Teh ,  Pawitter P. Bhatia ,  John P. Lee

发明人： Ramana Rachakonda ,  Lance E. Hacking ,  Mahesh K. Reddy ,  Lori R. Borger ,  Chee Hak Teh ,  Pawitter P. Bhatia ,  John P. Lee

IPC分类号： G06F13/40

CPC分类号： G06F13/40 ,  G01R31/318572 ,  G06F15/7807 ,  G06F15/7842 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic coupled to the interface logic, and a virtual firewall logic coupled between the chipset logic and the second core. The interface logic may include a firewall logic, a bus logic, and a test logic, and the chipset logic may include a memory controller to provide for communication with a memory coupled to the SoC. In some system implementations, both during test operations and functional operations, the second core can be disabled during normal operation to provide for a single core SoC, enabling greater flexibility of use of the SoC in many different implementations. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括具有第一和第二核心的系统级芯片（SoC），耦合到核心的接口逻辑，耦合到接口逻辑的芯片组逻辑以及耦合在芯片组逻辑之间的虚拟防火墙逻辑 和第二核心。 接口逻辑可以包括防火墙逻辑，总线逻辑和测试逻辑，并且芯片组逻辑可以包括存储器控制器以提供与耦合到SoC的存储器的通信。 在一些系统实现中，无论是在测试操作还是功能操作期间，在正常操作期间可以禁用第二个内核以提供单个核心SoC，从而在许多不同实现中使SoC的灵活性更高。 描述和要求保护其他实施例。

公开(公告)号：US5615969A

公开(公告)日：1997-04-01

申请号：US537627

申请日：1995-10-02

申请人： George Tunnicliffe ,  John P. Lee ,  Damian Dixon

发明人： George Tunnicliffe ,  John P. Lee ,  Damian Dixon

IPC分类号： B02C18/06 ,  F16D3/06 ,  B02C13/284 ,  F16C3/03

CPC分类号： B02C18/062 ,  F16D3/06 ,  Y10T403/7005 ,  Y10T403/7016

摘要： Disclosed is an adjustable length rotary drive coupling comprising a first rotary shaft provided with at least one tooth and a second rotary shaft provided with a plurality of abutment surfaces spaced apart along the length thereof associated with each the tooth. One of the rotary shafts is a drive shaft, with the other shaft being a driven shaft. Each tooth is selectively engageable with any of its associated abutment surfaces, to enable the length of the rotary drive coupling to be adjusted.

摘要翻译： 公开了一种可调节长度的旋转驱动联接器，包括设置有至少一个齿的第一旋转轴和设置有沿着与每个齿相关联的长度间隔开的多个邻接表面的第二旋转轴。 一个旋转轴是驱动轴，另一个轴是从动轴。 每个齿可选择性地与其相关的邻接表面中的任何一个接合，以使旋转驱动联轴器的长度能够被调节。

公开(公告)号：US08650629B2

公开(公告)日：2014-02-11

申请号：US12639258

申请日：2009-12-16

申请人： Ramana Rachakonda ,  Lance E. Hacking ,  Mahesh K. Reddy ,  Lori R. Borger ,  Chee Hak Teh ,  Pawitter P. Bhatia ,  John P. Lee

发明人： Ramana Rachakonda ,  Lance E. Hacking ,  Mahesh K. Reddy ,  Lori R. Borger ,  Chee Hak Teh ,  Pawitter P. Bhatia ,  John P. Lee

IPC分类号： G06F21/22

CPC分类号： G06F13/40 ,  G01R31/318572 ,  G06F15/7807 ,  G06F15/7842 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic coupled to the interface logic, and a virtual firewall logic coupled between the chipset logic and the second core. The interface logic may include a firewall logic, a bus logic, and a test logic, and the chipset logic may include a memory controller to provide for communication with a memory coupled to the SoC. In some system implementations, both during test operations and functional operations, the second core can be disabled during normal operation to provide for a single core SoC, enabling greater flexibility of use of the SoC in many different implementations. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括具有第一和第二核心的系统级芯片（SoC），耦合到核心的接口逻辑，耦合到接口逻辑的芯片组逻辑以及耦合在芯片组逻辑之间的虚拟防火墙逻辑 和第二核心。 接口逻辑可以包括防火墙逻辑，总线逻辑和测试逻辑，并且芯片组逻辑可以包括存储器控制器以提供与耦合到SoC的存储器的通信。 在一些系统实现中，无论是在测试操作还是功能操作期间，在正常操作期间可以禁用第二个内核以提供单个核心SoC，从而在许多不同实现中使SoC的灵活性更高。 描述和要求保护其他实施例。