Method and apparatus for rate-based cell traffic arbitration in a switch
    1.
    发明授权
    Method and apparatus for rate-based cell traffic arbitration in a switch 失效
    交换机中用于基于速率的小区业务仲裁的方法和装置

    公开(公告)号:US06512769B1

    公开(公告)日:2003-01-28

    申请号:US09090676

    申请日:1998-06-03

    IPC分类号: H04L1228

    摘要: A method and apparatus for rate-based cell traffic arbitration in a switch are provided, wherein arbitration is provided between eight traffic sources in the form of eight cell bus service modules on the same cell bus. A cell bus controller (CBC) is programmed with an 8-bit Relative Service Delay (RSD) value for each of the eight service modules. The value for each RSD is calculated based on the bandwidths allotted for each service module. This RSD value determines the portion of the total bandwidth of the switch platform reserved for the respective service module. Furthermore, each service module uses an 8-bit Service Delay Accumulator (SDA) register. The SDA register of each service module is configured using an SDA value, wherein the SDA register keeps track of when each of the service modules should receive service. The SDA value is calculated at each cell bus frame time for each of the service modules based on the RSD value for each of the service modules, a request for service, and the minimum SDA value among the service modules during a cell bus frame time. If the bandwidth is under-subscribed, the remaining bandwidth is shared among all eight service modules according to the RSD value of each service module. If the bandwidth is over-subscribed, each service module will have the assigned bandwidth portion decreased according to the RSD values.

    摘要翻译: 提供了一种用于交换机中基于速率的小区业务仲裁的方法和装置,其中在相同信元总线上以八个信元总线服务模块的形式在八个业务源之间提供仲裁。 单元总线控制器(CBC)被编程为八个服务模块中的每一个的8位相对服务延迟(RSD)值。 每个RSD的值根据为每个服务模块分配的带宽计算。 该RSD值确定为相应服务模块保留的交换机平台的总带宽的部分。 此外,每个服务模块使用8位服务延迟累加器(SDA)寄存器。 每个服务模块的SDA寄存器使用SDA值进行配置,其中SDA寄存器跟踪每个服务模块何时应该接收服务。 基于每个服务模块的RSD值,服务请求以及在信元总线帧时间期间服务模块中的最小SDA值,在每个服务模块的每个信元总线帧时间处计算SDA值。 如果带宽不足,则剩余带宽根据每个业务模块的RSD值在所有八个业务模块之间共享。 如果带宽超额订购,则每个服务模块将分配带宽部分根据RSD值减少。

    System for providing cell bus management in a switch platform including a write port cell count in each of a plurality of unidirectional FIFO for indicating which FIFO be able to accept more cell
    2.
    发明授权
    System for providing cell bus management in a switch platform including a write port cell count in each of a plurality of unidirectional FIFO for indicating which FIFO be able to accept more cell 失效
    用于在交换机平台中提供信元总线管理的系统,包括在多个单向FIFO中的每一个中的写入端口单元计数,用于指示哪个FIFO能够接受更多的单元

    公开(公告)号:US06463485B1

    公开(公告)日:2002-10-08

    申请号:US09089881

    申请日:1998-06-03

    IPC分类号: G06F1314

    摘要: A method and apparatus for providing cell bus management in a switch platform are provided. Each unidirectional FIFO buffer of a cell bus controller outputs a write port cell count from a write port. A cell count value is programmed at which the write port cell count is outputted. When the write port cell count indicates that the FIFO buffer can not accept additional data or cells, a master bidirectional FIFO unit ceases reading cells to a unidirectional FIFO buffer of the slave bidirectional FIFO unit in response to the write port cell count. Furthermore, the master bidirectional FIFO unit disables a corresponding switch from routing cells to the slave bidirectional FIFO unit in response to the write port cell count; the switch routes the cells to another of the slave bidirectional FIFO units. The master bidirectional FIFO unit resumes reading cells to the second unidirectional FIFO buffer of the slave bidirectional FIFO unit in response to a write port cell count indication that the FIFO buffer can accept additional data or cells. In response, the master bidirectional FIFO unit enables an associated switch to route cells to the slave bidirectional FIFO unit.

    摘要翻译: 提供了一种用于在交换平台中提供信元总线管理的方法和装置。 单元总线控制器的每个单向FIFO缓冲器从写入端口输出写入端口单元计数。 编程单元计数值,输出写入端口单元计数。 当写入端口单元计数指示FIFO缓冲器不能接受附加数据或单元时,响应于写入端口单元计数,主双向FIFO单元停止将单元读取到从双向FIFO单元的单向FIFO缓冲器。 此外,主双向FIFO单元响应于写入端口单元计数禁用从路由单元到从双向FIFO单元的相应交换机; 交换机将单元路由到另一个从属双向FIFO单元。 响应于FIFO缓冲器可以接受附加数据或单元的写入口单元计数指示,主双向FIFO单元恢复读取单元到从双向FIFO单元的第二单向FIFO缓冲器。 作为响应,主双向FIFO单元使相关联的开关将单元路由到从属双向FIFO单元。

    Method and apparatus for providing asynchronous memory functions for bi-directional traffic in a switch platform
    3.
    发明授权
    Method and apparatus for providing asynchronous memory functions for bi-directional traffic in a switch platform 失效
    用于在交换平台中为双向业务提供异步存储器功能的方法和装置

    公开(公告)号:US06438102B1

    公开(公告)日:2002-08-20

    申请号:US09090299

    申请日:1998-06-03

    IPC分类号: G01R3108

    摘要: A method and apparatus for providing asynchronous memory functions for bi-directional cell traffic in a switch platform are provided, wherein a parameterized bi-directional FIFO unit controls cell traffic in a switch platform using a first and a second unidirectional FIFO buffer. The first and second unidirectional FIFO buffers each comprises asynchronous read and write ports. A cell size and a word size of the first and second unidirectional FIFO buffers are programmable. The bi-directional FIFO unit is coupled to write at least one cell from and read at least one cell to at lest one asynchronous transfer mode (ATM) interface, at least one frame relay interface, at least one voice interface, and at least one data interface. As such, the first unidirectional FIFO buffer is coupled to write at least one cell from, and the second unidirectional FIFO buffer is coupled to read at least one cell to an ATM interface, a frame relay interface, a voice interface, and a data interface. The first unidirectional FIFO buffer is coupled to read at least one cell to at least one switch, and the second unidirectional FIFO buffer is coupled to write at least one cell from at least one switch, wherein the switch handles cells from sources having a number of bandwidths. The switch is coupled to route the at least one cell between an OC12 trunk line and at least one service module. The service module is coupled to provide the cell to at least one service subscriber using T1, E1, T3, E3, TC3, and OC 12 ports.

    摘要翻译: 提供了一种用于在交换平台中为双向小区业务提供异步存储器功能的方法和装置,其中参数化双向FIFO单元使用第一和第二单向FIFO缓冲器来控制交换平台中的小区业务。 第一和第二单向FIFO缓冲器包括异步读取和写入端口。 第一和第二单向FIFO缓冲器的单元大小和单词大小是可编程的。 双向FIFO单元被耦合以从至少一个小区写入至少一个小区,至少读取一个小区至少一个异步传输模式(ATM)接口,至少一个帧中继接口,至少一个语音接口和至少一个 数据接口。 这样,第一单向FIFO缓冲器被耦合以写入至少一个单元,并且第二单向FIFO缓冲器被耦合以将至少一个单元读取到ATM接口,帧中继接口,语音接口和数据接口 。 耦合第一单向FIFO缓冲器以将至少一个单元读取到至少一个开关,并且第二单向FIFO缓冲器被耦合以从至少一个开关写入至少一个单元,其中该开关处理来自具有多个 带宽。 交换机被耦合以在OC12中继线与至少一个服务模块之间路由至少一个小区。 服务模块被耦合以将小区提供给使用T1,E1,T3,E3,TC3和OC12端口的至少一个服务订户。

    Method and apparatus for providing programmable memory functions for bi-directional traffic in a switch platform
    4.
    发明授权
    Method and apparatus for providing programmable memory functions for bi-directional traffic in a switch platform 失效
    用于为交换平台中的双向业务提供可编程存储器功能的方法和装置

    公开(公告)号:US06967961B1

    公开(公告)日:2005-11-22

    申请号:US09090096

    申请日:1998-06-03

    IPC分类号: H04L12/56

    摘要: A method and apparatus for providing programmable memory functions for bi-directional cell traffic in a switch platform are provided, wherein a parameterized bi-directional FIFO unit controls cell traffic in a switch platform using a first and a second unidirectional FIFO buffer. The first and second unidirectional FIFO buffers each comprise asynchronous read and write ports. A cell size and a word size of the first and second unidirectional FIFO buffers are programmable. The bi-directional FIFO unit is coupled to write at least one cell from and read at least one cell to at least one asynchronous transfer mode (ATM) interface, at least one frame relay interface, at least one voice interface, and at least one data interface. As such, the first unidirectional FIFO buffer is coupled to write at least one cell from, and the second unidirectional FIFO buffer is coupled to read at least one cell to an ATM interface, a frame relay interface, a voice interface, and a data interface. The first unidirectional FIFO buffer is coupled to read at least one cell to at least one switch, and the second unidirectional FIFO buffer is coupled to write at least one cell from at least one switch, wherein the switch handles cells from sources having a number of bandwidths. The switch is coupled to route the at least one cell between an OC12 trunk line and at least one service module. The service module is coupled to provide the cell to at least one service subscriber using T1, E1, T3, E3, OC3, and OC 12 ports.

    摘要翻译: 提供了一种用于在交换平台中为双向小区业务提供可编程存储器功能的方法和装置,其中参数化双向FIFO单元使用第一和第二单向FIFO缓冲器来控制交换平台中的小区业务。 第一和第二单向FIFO缓冲器各自包括异步读取和写入端口。 第一和第二单向FIFO缓冲器的单元大小和单词大小是可编程的。 双向FIFO单元被耦合以从至少一个小区写入至少一个小区,并将其读取到至少一个异步传输模式(ATM)接口,至少一个帧中继接口,至少一个语音接口和至少一个 数据接口。 这样,第一单向FIFO缓冲器被耦合以写入至少一个单元,并且第二单向FIFO缓冲器被耦合以将至少一个单元读取到ATM接口,帧中继接口,语音接口和数据接口 。 耦合第一单向FIFO缓冲器以将至少一个单元读取到至少一个开关,并且第二单向FIFO缓冲器被耦合以从至少一个开关写入至少一个单元,其中该开关处理来自具有多个 带宽。 交换机被耦合以在OC12中继线与至少一个服务模块之间路由至少一个小区。 服务模块被耦合以将小区提供给使用T1,E1,T3,E3,OC3和OC12端口的至少一个服务订户。

    Method and apparatus for routing cells having different formats among service modules of a switch platform
    5.
    发明授权
    Method and apparatus for routing cells having different formats among service modules of a switch platform 失效
    用于在交换平台的服务模块之间路由具有不同格式的小区的方法和装置

    公开(公告)号:US06483850B1

    公开(公告)日:2002-11-19

    申请号:US09090300

    申请日:1998-06-03

    IPC分类号: H04J316

    摘要: A method and apparatus for routing cells having different formats among service modules of a switch platform are provided. The cells are routed among service modules of a switch by a cell bus controller (CBC) using a first memory to convert an address having a first format into an address having a second format. The address having the first format is received in a header of a cell, and the address format comprises a 17-bit cell bus logical connection number of a destination port. The address having the second format is a 16-bit UDF used by a switch of the switch platform. The address having the first format is used to form a third address that is used to access the first memory. The data located at the third address of the first memory is a 16-bit UDF used to address the switch. A second memory is used to convert an address having the second format into an address having the first format. The address having the second format is used as a fourth address to access the second memory. The data located at the fourth address of the second memory is a 32-bit cell bus header that addresses a destination port. The destination port is at least one service module of the switch platform. The first and second memory comprise an external random access memory.

    摘要翻译: 提供了一种用于在交换平台的服务模块之间路由具有不同格式的小区的方法和装置。 这些小区由信元总线控制器(CBC)使用第一存储器路由到交换机的服务模块之间,以将具有第一格式的地址转换为具有第二格式的地址。 具有第一格式的地址被接收在小区的头部中,并且地址格式包括目的地端口的17比特单元总线逻辑连接号码。 具有第二格式的地址是由交换机平台的交换机使用的16位UDF。 具有第一格式的地址用于形成用于访问第一存储器的第三地址。 位于第一个存储器第三个地址的数据是一个16位UDF,用于对交换机进行寻址。 第二存储器用于将具有第二格式的地址转换成具有第一格式的地址。 具有第二格式的地址被用作访问第二存储器的第四地址。 位于第二存储器的第四地址的数据是寻址目的地端口的32位单元总线头。 目标端口是交换机平台的至少一个服务模块。 第一和第二存储器包括外部随机存取存储器。

    Variably delayable transmission of packets between independently clocked source, intermediate, and destination circuits while maintaining orderly and timely processing in one or both of the intermediate and destination circuits
    8.
    发明申请
    Variably delayable transmission of packets between independently clocked source, intermediate, and destination circuits while maintaining orderly and timely processing in one or both of the intermediate and destination circuits 有权
    在独立时钟的源,中间和目的地电路之间可变地延迟分组的传输,同时在中间和目的电路中的一个或两个中保持有序和及时的处理

    公开(公告)号:US20070130246A1

    公开(公告)日:2007-06-07

    申请号:US11699737

    申请日:2007-01-29

    IPC分类号: G06F15/16

    CPC分类号: G06F1/14 H04L2012/5674

    摘要: In a system having independently-clocked job-performing circuits (e.g., payload processors) and independently-clocked job-ordering circuits (e.g., request and payload suppliers), coordinating mechanisms are provided for coordinating exchanges between the independently-clocked circuits. The coordinating mechanisms include those that use transmitted time-stamps for scheduling contention-free performances within the job-performing circuits of requested jobs. The coordinating mechanisms additionally or alternatively include static and dynamic rate constraining means that are configured to prevent a faster-clocked one of the independently-clocked circuits from overwhelming a more slowly-clocked other of the independently-clocked circuits. In one implementation, independently-clocked telecommunication-shelves house a distributed set of line cards and switch cards. An asynchronous interconnect is provided between the independently-clocked shelves for carrying job requests and payload data between the distributed line cards and the distributed switch cards. The multi-shelf system is scalable and robust because additional or replacement line and switch cards may be inserted into one or another of the independently-clocked shelves as desired and because a unified clock-tree is not needed for synchronizing activities within the interconnected, but independently clocked shelves.

    摘要翻译: 在具有独立时钟的作业执行电路(例如,有效载荷处理器)和独立时钟的作业排序电路(例如,请求和有效载荷供应商)的系统中,提供协调机制以协调独立时钟的电路之间的交换。 协调机制包括使用传输的时间戳来调度所请求作业的作业执行电路内的无竞争性能的那些机制。 协调机构附加地或备选地包括静态和动态速率限制装置,其被配置为防止更快时钟的一个独立时钟的电路压倒更独立时钟的电路中更慢时钟的其他电路。 在一个实现中,独立时钟的电信货架容纳一组分布式的线卡和交换卡。 在独立时钟的架之间提供异步互连,用于在分布式线路卡和分布式交换卡之间传送作业请求和有效载荷数据。 多架系统是可扩展的和可靠的,因为可以根据需要将额外的或更换的线路和交换机卡插入独立时钟的架子中的一个或另一个,并且因为不需要统一的时钟树来同步互连的活动,而是 独立时钟的货架。

    Scheme for maintaining synchronization in an inherently asynchronous system
    9.
    发明授权
    Scheme for maintaining synchronization in an inherently asynchronous system 失效
    用于在固有异步系统中维护同步的方案

    公开(公告)号:US06898211B1

    公开(公告)日:2005-05-24

    申请号:US09334693

    申请日:1999-06-16

    IPC分类号: H04J3/06

    CPC分类号: H04J3/0697

    摘要: A synchronization state for a local clock generating circuit of a first of a number of components of a distributed system is maintained according to a number of local clock cycles recorded between successive occurrences of a global synchronization signal provided to the components within the distributed system. The local clock generating circuit may enters the synchronization state only after observing a predetermined number of occurrences of successive local clock cycles between instances of the global synchronization signal. The local clock generating circuit continues to provide local control signals for the first of the components at time instants corresponding to the number of local clock cycles even after an instance of the global synchronization signal is observed at a time instant corresponding to one local clock cycle more or less than the number of local clock cycles. However, the local clock generating circuit enters an alarm state when the global synchronization signal is observed at time instants corresponding to more than one local clock cycle more or less than the number of local clock cycles.

    摘要翻译: 根据在分布式系统中提供给组件的全局同步信号的连续出现之间记录的本地时钟周期的数量来保持分布式系统的多个组件中的第一个组件的本地时钟发生电路的同步状态。 本地时钟发生电路只有在观察到全局同步信号的实例之间的连续本地时钟周期的预定次数的出现之后,才能进入同步状态。 本地时钟发生电路继续在对应于本地时钟周期的数量的时刻在第一个分量提供本地控制信号,即使在对应于一个本地时钟周期的时间点观察到全局同步信号的一个实例之后 或小于本地时钟周期的数量。 然而,当在多于或多于本地时钟周期的多于一个本地时钟周期的时刻观察全局同步信号时,本地时钟发生电路进入报警状态。