公开(公告)号：US07642101B2

公开(公告)日：2010-01-05

申请号：US11567055

申请日：2006-12-05

申请人： George Liu ,  Vencent Chang ,  Chin-Hsiang Lin ,  Kuei Shun Chen ,  Norman Chen

发明人： George Liu ,  Vencent Chang ,  Chin-Hsiang Lin ,  Kuei Shun Chen ,  Norman Chen

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： H01L23/544 ,  G03F7/70625 ,  G03F7/70641 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is fabricated to include one or more sets of calibration patterns used to measure line pitch and line focus.

摘要翻译： 制造半导体器件以包括用于测量线间距和线焦点的一组或多组校准图案。

公开(公告)号：US07387969B2

公开(公告)日：2008-06-17

申请号：US11084495

申请日：2005-03-18

申请人： George Liu ,  Vencent Chang ,  Norman Chen ,  Yao-Ching Ku ,  Chin-Hsiang Lin ,  Kuei Shun Chen

发明人： George Liu ,  Vencent Chang ,  Norman Chen ,  Yao-Ching Ku ,  Chin-Hsiang Lin ,  Kuei Shun Chen

IPC分类号： H01L21/302

CPC分类号： H01L21/31144 ,  G03F7/11 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/76807

摘要： A patterned hardmask and method for forming the same, the method including providing a substrate comprising an overlying resist sensitive to activating radiation; forming an overlying hardmask insensitive to the activating radiation; exposing the resist through the hardmask to the activating radiation; baking the resist and the hardmask; and, developing the hardmask and resist to form a patterned resist and patterned hardmask.

摘要翻译： 一种图案化硬掩模及其形成方法，所述方法包括提供包含对活化辐射敏感的上覆抗蚀剂的基底; 形成对激活辐射不敏感的上覆硬掩模; 将抗蚀剂通过硬掩模暴露于活化辐射; 烘烤抗蚀剂和硬掩模; 并开发硬掩模和抗蚀剂以形成图案化的抗蚀剂和图案化的硬掩模。

公开(公告)号：US20080128924A1

公开(公告)日：2008-06-05

申请号：US11567055

申请日：2006-12-05

申请人： George Liu ,  Vencent Chang ,  Chin-Hsiang Lin ,  Kuei Shun Chen ,  Norman Chen

发明人： George Liu ,  Vencent Chang ,  Chin-Hsiang Lin ,  Kuei Shun Chen ,  Norman Chen

IPC分类号： H01L23/544 ,  H01L21/66 ,  G03F7/20

CPC分类号： H01L23/544 ,  G03F7/70625 ,  G03F7/70641 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is fabricated to include one or more sets of calibration patterns used to measure line pitch and line focus.

摘要翻译： 制造半导体器件以包括用于测量线间距和线焦点的一组或多组校准图案。

公开(公告)号：US08472005B2

公开(公告)日：2013-06-25

申请号：US11677693

申请日：2007-02-22

申请人： George Liu ,  Kuei Shun Chen ,  Norman Chen ,  Vencent Chang ,  Chin-Hsiang Lin

发明人： George Liu ,  Kuei Shun Chen ,  Norman Chen ,  Vencent Chang ,  Chin-Hsiang Lin

IPC分类号： G03B27/54

CPC分类号： G03F7/70425 ,  G03F7/701

摘要： System and method for enhancing optical lithography methodology for hole patterning in semiconductor fabrication are described. In one embodiment, a photolithography system comprises an illumination system for conditioning light from a light source, the illumination system producing a three-pore illumination pattern; a reticle comprising at least a portion of a pattern to be imaged onto a substrate, wherein the three-pore illumination pattern produced by the illumination system is projected through the reticle; and a projection lens disposed between the reticle and the substrate.

摘要翻译： 描述了用于增强半导体制造中的孔图案化的光学光刻方法的系统和方法。 在一个实施例中，光刻系统包括用于调节来自光源的光的照明系统，所述照明系统产生三孔照明图案; 包括至少一部分要成像到基底上的图案的掩模版，其中由照明系统产生的三孔照明图案通过掩模版投射; 以及设置在掩模版和基板之间的投影透镜。

公开(公告)号：US20080204688A1

公开(公告)日：2008-08-28

申请号：US11677693

申请日：2007-02-22

申请人： George Liu ,  Kuei Shun Chen ,  Norman Chen ,  Vencent Chang ,  Chin-Hsiang Lin

发明人： George Liu ,  Kuei Shun Chen ,  Norman Chen ,  Vencent Chang ,  Chin-Hsiang Lin

IPC分类号： G03B27/54

CPC分类号： G03F7/70425 ,  G03F7/701

摘要： System and method for enhancing optical lithography methodology for hole patterning in semiconductor fabrication are described. In one embodiment, a photolithography system comprises an illumination system for conditioning light from a light source, the illumination system producing a three-pore illumination pattern; a reticle comprising at least a portion of a pattern to be imaged onto a substrate, wherein the three-pore illumination pattern produced by the illumination system is projected through the reticle; and a projection lens disposed between the reticle and the substrate.

摘要翻译： 描述了用于增强半导体制造中的孔图案化的光学光刻方法的系统和方法。 在一个实施例中，光刻系统包括用于调节来自光源的光的照明系统，所述照明系统产生三孔照明图案; 包括至少一部分要成像到基底上的图案的掩模版，其中由照明系统产生的三孔照明图案通过掩模版投射; 以及设置在掩模版和基板之间的投影透镜。

公开(公告)号：US09091923B2

公开(公告)日：2015-07-28

申请号：US11677879

申请日：2007-02-22

申请人： George Liu ,  Vencent Chang ,  Norman Chen ,  Kuei Shun Chen ,  Chin-Hsiang Lin

发明人： George Liu ,  Vencent Chang ,  Norman Chen ,  Kuei Shun Chen ,  Chin-Hsiang Lin

IPC分类号： G03F1/00 ,  G03F7/20 ,  G03F7/004

CPC分类号： G03F1/144 ,  G03F1/70 ,  G03F7/0045 ,  G03F7/2022 ,  G03F7/70475

摘要： Contrast enhancing exposure apparatus and method for use in semiconductor fabrication are described. In one embodiment, a method for forming a pattern on a substrate, wherein the substrate includes a photoresist layer comprising photoacid generators (“PAGs”) and photobase generators (“PBGs”), is described. The method includes dividing the pattern into two component patterns; exposing the photoresist layer of the substrate to UV light through a first mask corresponding to a first one of the component patterns; subsequent to the exposing the photoresist layer of the substrate to UV light through the first mask, exposing the photoresist layer of the substrate to UV light through a second mask corresponding to a second one of the component patterns, wherein the PAGs and PBGs disposed in areas of the photoresist layer that have been exposed to UV light at least twice are activated and wherein the activated PAGs neutralize the activated PBGs in areas of the photoresist layer that have been exposed to UV light at least twice.

摘要翻译： 描述了用于半导体制造的对比增强曝光装置和方法。 在一个实施例中，描述了在衬底上形成图案的方法，其中衬底包括包含光酸发生器（“PAG”）和光产生器（“PBG”）的光致抗蚀剂层。 该方法包括将图案划分成两个分量图案; 通过与第一组分图案相对应的第一掩模将衬底的光致抗蚀剂层暴露于UV光; 在将衬底的光致抗蚀剂层暴露于通过第一掩模的UV光之后，通过对应于第二组件图案的第二掩模将衬底的光致抗蚀剂层暴露于UV光，其中设置在区域中的PAG和PBG 已经暴露于UV光的光致抗蚀剂层至少两次被激活，并且其中激活的PAG在已经暴露于UV光的光致抗蚀剂层的区域中中和活化的PBG至少两次。

公开(公告)号：US20080206679A1

公开(公告)日：2008-08-28

申请号：US11677879

申请日：2007-02-22

申请人： George Liu ,  Vencent Chang ,  Norman Chen ,  Kuei Shun Chen ,  Chin-Hsiang Lin

发明人： George Liu ,  Vencent Chang ,  Norman Chen ,  Kuei Shun Chen ,  Chin-Hsiang Lin

IPC分类号： G03F1/02

CPC分类号： G03F1/144 ,  G03F1/70 ,  G03F7/0045 ,  G03F7/2022 ,  G03F7/70475

摘要： Contrast enhancing exposure apparatus and method for use in semiconductor fabrication are described. In one embodiment, a method for forming a pattern on a substrate, wherein the substrate includes a photoresist layer comprising photoacid generators (“PAGs”) and photobase generators (“PBGs”), is described. The method includes dividing the pattern into two component patterns; exposing the photoresist layer of the substrate to UV light through a first mask corresponding to a first one of the component patterns; subsequent to the exposing the photoresist layer of the substrate to UV light through the first mask, exposing the photoresist layer of the substrate to UV light through a second mask corresponding to a second one of the component patterns, wherein the PAGs and PBGs disposed in areas of the photoresist layer that have been exposed to UV light at least twice are activated and wherein the activated PAGs neutralize the activated PBGs in areas of the photoresist layer that have been exposed to UV light at least twice.

摘要翻译： 描述了用于半导体制造的对比增强曝光装置和方法。 在一个实施例中，描述了在衬底上形成图案的方法，其中衬底包括包含光酸发生器（“PAG”）和光产生器（“PBG”）的光致抗蚀剂层。 该方法包括将图案划分成两个分量图案; 通过与第一组分图案相对应的第一掩模将衬底的光致抗蚀剂层暴露于UV光; 在将衬底的光致抗蚀剂层暴露于通过第一掩模的UV光之后，通过对应于第二组件图案的第二掩模将衬底的光致抗蚀剂层暴露于UV光，其中设置在区域中的PAG和PBG 已经暴露于UV光的光致抗蚀剂层至少两次被激活，并且其中激活的PAG在已经暴露于UV光的光致抗蚀剂层的区域中中和活化的PBG至少两次。

公开(公告)号：US07960821B2

公开(公告)日：2011-06-14

申请号：US12716980

申请日：2010-03-03

申请人： Kuei Shun Chen ,  Chin-Hsiang Lin ,  Vencent Chang ,  Lawrence Lin ,  Lai Chien Wen ,  Jhun Hua Chen

发明人： Kuei Shun Chen ,  Chin-Hsiang Lin ,  Vencent Chang ,  Lawrence Lin ,  Lai Chien Wen ,  Jhun Hua Chen

IPC分类号： H01L21/00

CPC分类号： H01L21/76811 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/7684 ,  H01L23/522 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device and method of making the integrated circuit device are disclosed. An exemplary apparatus includes: a semiconductor layer; and a dielectric layer on the semiconductor layer, the dielectric layer having conductive vias and dummy vias formed therein, wherein the conductive vias and dummy vias extend varying distances into the dielectric layer, the conductive vias extending through the dielectric layer to the semiconductor layer, and the dummy vias extending through the dielectric layer to a distance above the semiconductor layer.

摘要翻译： 公开了一种集成电路器件及其制造方法。 示例性装置包括：半导体层; 以及在该半导体层上的电介质层，该电介质层具有形成在其中的导电通孔和虚拟通孔，其中该导电通路和虚拟通孔将延伸到该介电层的变化距离，该导电通孔延伸穿过该介电层至该半导体层，以及 虚拟通孔延伸穿过介电层到半导体层上方一段距离。

公开(公告)号：US20060211254A1

公开(公告)日：2006-09-21

申请号：US11084495

申请日：2005-03-18

申请人： George Liu ,  Vencent Chang ,  Norman Chen ,  Yao-Ching Ku ,  Chin-Hsiang Lin ,  Kuei Chen

发明人： George Liu ,  Vencent Chang ,  Norman Chen ,  Yao-Ching Ku ,  Chin-Hsiang Lin ,  Kuei Chen

IPC分类号： H01L21/467 ,  G03F1/00

CPC分类号： H01L21/31144 ,  G03F7/11 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/76807

摘要： A patterned hardmask and method for forming the same, the method including providing a substrate comprising an overlying resist sensitive to activating radiation; forming an overlying hardmask insensitive to the activating radiation; exposing the resist through the hardmask to the activating radiation; baking the resist and the hardmask; and, developing the hardmask and resist to form a patterned resist and patterned hardmask.

摘要翻译： 一种图案化硬掩模及其形成方法，所述方法包括提供包含对活化辐射敏感的上覆抗蚀剂的基底; 形成对激活辐射不敏感的上覆硬掩模; 将抗蚀剂通过硬掩模暴露于活化辐射; 烘烤抗蚀剂和硬掩模; 并开发硬掩模和抗蚀剂以形成图案化的抗蚀剂和图案化的硬掩模。

公开(公告)号：US07767570B2

公开(公告)日：2010-08-03

申请号：US11457032

申请日：2006-07-12

申请人： Kuei Shun Chen ,  Chin-Hsiang Lin ,  Vencent Chang ,  Lawrence Lin ,  Lai Chien Wen ,  Jhun Hua Chen

发明人： Kuei Shun Chen ,  Chin-Hsiang Lin ,  Vencent Chang ,  Lawrence Lin ,  Lai Chien Wen ,  Jhun Hua Chen

IPC分类号： H01L21/00

CPC分类号： H01L21/76811 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/7684 ,  H01L23/522 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of making an integrated circuit includes providing a low-k dielectric layer on a substrate, the low-k dielectric layer including or adjacent to a plurality of conductive features; patterning the low-k dielectric layer to form trenches; patterning the low-k dielectric layer to form conductive vias and dummy vias, wherein each of the conductive vias is aligned with at least one of the plurality of the conductive features and at least one of the trenches, and each of the dummy vias is a distance above the plurality of conductive features; filling the trenches, conductive vias, and dummy vias using one or more conductive materials; and planarizing the conductive material(s).

摘要翻译： 制造集成电路的方法包括在衬底上提供低k电介质层，低k电介质层包括或邻近多个导电特征; 图案化低k电介质层以形成沟槽; 图案化低k电介质层以形成导电通孔和虚拟通孔，其中每个导电通孔与多个导电特征和至少一个沟槽中的至少一个对准，并且每个虚拟通孔为 在多个导电特征之上的距离; 使用一种或多种导电材料填充沟槽，导电通孔和虚拟通孔; 并平坦化导电材料。