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    Dummy vias for damascene process
    3.
    发明授权
    Dummy vias for damascene process 有权
    用于大马士革过程的虚拟通孔

    公开(公告)号：US07767570B2

    公开(公告)日：2010-08-03

    申请号：US11457032

    申请日：2006-07-12

    申请人： Kuei Shun Chen ,  Chin-Hsiang Lin ,  Vencent Chang ,  Lawrence Lin ,  Lai Chien Wen ,  Jhun Hua Chen

    发明人： Kuei Shun Chen ,  Chin-Hsiang Lin ,  Vencent Chang ,  Lawrence Lin ,  Lai Chien Wen ,  Jhun Hua Chen

    IPC分类号： H01L21/00

    CPC分类号： H01L21/76811 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/7684 ,  H01L23/522 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of making an integrated circuit includes providing a low-k dielectric layer on a substrate, the low-k dielectric layer including or adjacent to a plurality of conductive features; patterning the low-k dielectric layer to form trenches; patterning the low-k dielectric layer to form conductive vias and dummy vias, wherein each of the conductive vias is aligned with at least one of the plurality of the conductive features and at least one of the trenches, and each of the dummy vias is a distance above the plurality of conductive features; filling the trenches, conductive vias, and dummy vias using one or more conductive materials; and planarizing the conductive material(s).

    摘要翻译： 制造集成电路的方法包括在衬底上提供低k电介质层，低k电介质层包括或邻近多个导电特征; 图案化低k电介质层以形成沟槽; 图案化低k电介质层以形成导电通孔和虚拟通孔，其中每个导电通孔与多个导电特征和至少一个沟槽中的至少一个对准，并且每个虚拟通孔为 在多个导电特征之上的距离; 使用一种或多种导电材料填充沟槽，导电通孔和虚拟通孔; 并平坦化导电材料。

    Methodology for implementing enhanced optical lithography for hole patterning in semiconductor fabrication
    7.
    发明授权
    Methodology for implementing enhanced optical lithography for hole patterning in semiconductor fabrication 有权
    实现半导体制造中孔图案化的增强型光刻技术的方法

    公开(公告)号：US08472005B2

    公开(公告)日：2013-06-25

    申请号：US11677693

    申请日：2007-02-22

    申请人： George Liu ,  Kuei Shun Chen ,  Norman Chen ,  Vencent Chang ,  Chin-Hsiang Lin

    发明人： George Liu ,  Kuei Shun Chen ,  Norman Chen ,  Vencent Chang ,  Chin-Hsiang Lin

    IPC分类号： G03B27/54

    CPC分类号： G03F7/70425 ,  G03F7/701

    摘要： System and method for enhancing optical lithography methodology for hole patterning in semiconductor fabrication are described. In one embodiment, a photolithography system comprises an illumination system for conditioning light from a light source, the illumination system producing a three-pore illumination pattern; a reticle comprising at least a portion of a pattern to be imaged onto a substrate, wherein the three-pore illumination pattern produced by the illumination system is projected through the reticle; and a projection lens disposed between the reticle and the substrate.

    摘要翻译： 描述了用于增强半导体制造中的孔图案化的光学光刻方法的系统和方法。 在一个实施例中，光刻系统包括用于调节来自光源的光的照明系统，所述照明系统产生三孔照明图案; 包括至少一部分要成像到基底上的图案的掩模版，其中由照明系统产生的三孔照明图案通过掩模版投射; 以及设置在掩模版和基板之间的投影透镜。

    Methodology For Implementing Enhanced Optical Lithography For Hole Patterning In Semiconductor Fabrication
    8.
    发明申请
    Methodology For Implementing Enhanced Optical Lithography For Hole Patterning In Semiconductor Fabrication 有权
    在半导体制造中实现孔图案的增强光刻法的方法

    公开(公告)号：US20080204688A1

    公开(公告)日：2008-08-28

    申请号：US11677693

    申请日：2007-02-22

    申请人： George Liu ,  Kuei Shun Chen ,  Norman Chen ,  Vencent Chang ,  Chin-Hsiang Lin

    发明人： George Liu ,  Kuei Shun Chen ,  Norman Chen ,  Vencent Chang ,  Chin-Hsiang Lin

    IPC分类号： G03B27/54

    CPC分类号： G03F7/70425 ,  G03F7/701

    摘要： System and method for enhancing optical lithography methodology for hole patterning in semiconductor fabrication are described. In one embodiment, a photolithography system comprises an illumination system for conditioning light from a light source, the illumination system producing a three-pore illumination pattern; a reticle comprising at least a portion of a pattern to be imaged onto a substrate, wherein the three-pore illumination pattern produced by the illumination system is projected through the reticle; and a projection lens disposed between the reticle and the substrate.

    摘要翻译： 描述了用于增强半导体制造中的孔图案化的光学光刻方法的系统和方法。 在一个实施例中，光刻系统包括用于调节来自光源的光的照明系统，所述照明系统产生三孔照明图案; 包括至少一部分要成像到基底上的图案的掩模版，其中由照明系统产生的三孔照明图案通过掩模版投射; 以及设置在掩模版和基板之间的投影透镜。

    Method and System For Making Photo-Resist Patterns
    9.
    发明申请
    Method and System For Making Photo-Resist Patterns 审中-公开
    制作防光图案的方法和系统

    公开(公告)号：US20080102648A1

    公开(公告)日：2008-05-01

    申请号：US11555558

    申请日：2006-11-01

    申请人： Chin-Hsiang Lin ,  Hsiao-Tzu Lu ,  Kuei Shun Chen ,  Ching-Yu Chang ,  Vencent Chang

    发明人： Chin-Hsiang Lin ,  Hsiao-Tzu Lu ,  Kuei Shun Chen ,  Ching-Yu Chang ,  Vencent Chang

    IPC分类号： H01L21/302 ,  G03G13/10

    CPC分类号： H01L21/0271 ,  G03F7/095

    摘要： A method of forming a resist pattern in a semiconductor device layer includes forming a buffer layer on a semiconductor device layer and forming a resist layer on the buffer layer. A decomposing agent is released into a portion of the buffer layer by a portion of the resist layer whereupon the portion of the buffer layer and the portion of the resist layer are removed to form a process window substantially free of resist residue that can be subsequently exploited for etching of the semiconductor device layer.

    摘要翻译： 在半导体器件层中形成抗蚀剂图案的方法包括在半导体器件层上形成缓冲层，并在缓冲层上形成抗蚀剂层。 分解剂通过抗蚀剂层的一部分释放到缓冲层的一部分中，随后缓冲层的部分和抗蚀剂层的一部分被去除以形成基本上不含抗蚀剂残留物的工艺窗口，其可以被随后利用 用于蚀刻半导体器件层。

    Contrast enhancing exposure system and method for use in semiconductor fabrication
    10.
    发明授权
    Contrast enhancing exposure system and method for use in semiconductor fabrication 有权
    对比增强曝光系统和半导体制造中使用的方法

    公开(公告)号：US09091923B2

    公开(公告)日：2015-07-28

    申请号：US11677879

    申请日：2007-02-22

    申请人： George Liu ,  Vencent Chang ,  Norman Chen ,  Kuei Shun Chen ,  Chin-Hsiang Lin

    发明人： George Liu ,  Vencent Chang ,  Norman Chen ,  Kuei Shun Chen ,  Chin-Hsiang Lin

    IPC分类号： G03F1/00 ,  G03F7/20 ,  G03F7/004

    CPC分类号： G03F1/144 ,  G03F1/70 ,  G03F7/0045 ,  G03F7/2022 ,  G03F7/70475

    摘要： Contrast enhancing exposure apparatus and method for use in semiconductor fabrication are described. In one embodiment, a method for forming a pattern on a substrate, wherein the substrate includes a photoresist layer comprising photoacid generators (“PAGs”) and photobase generators (“PBGs”), is described. The method includes dividing the pattern into two component patterns; exposing the photoresist layer of the substrate to UV light through a first mask corresponding to a first one of the component patterns; subsequent to the exposing the photoresist layer of the substrate to UV light through the first mask, exposing the photoresist layer of the substrate to UV light through a second mask corresponding to a second one of the component patterns, wherein the PAGs and PBGs disposed in areas of the photoresist layer that have been exposed to UV light at least twice are activated and wherein the activated PAGs neutralize the activated PBGs in areas of the photoresist layer that have been exposed to UV light at least twice.

    摘要翻译： 描述了用于半导体制造的对比增强曝光装置和方法。 在一个实施例中，描述了在衬底上形成图案的方法，其中衬底包括包含光酸发生器（“PAG”）和光产生器（“PBG”）的光致抗蚀剂层。 该方法包括将图案划分成两个分量图案; 通过与第一组分图案相对应的第一掩模将衬底的光致抗蚀剂层暴露于UV光; 在将衬底的光致抗蚀剂层暴露于通过第一掩模的UV光之后，通过对应于第二组件图案的第二掩模将衬底的光致抗蚀剂层暴露于UV光，其中设置在区域中的PAG和PBG 已经暴露于UV光的光致抗蚀剂层至少两次被激活，并且其中激活的PAG在已经暴露于UV光的光致抗蚀剂层的区域中中和活化的PBG至少两次。