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公开(公告)号：US07650455B2
公开(公告)日：2010-01-19
申请号：US11829250
申请日：2007-07-27
申请人： Gerald K. Bartley , Darryl J. Becker , John M. Borkenhagen , Paul E. Dahlen , Philip R. Germann , William P. Hovis , Mark O. Maxson
发明人： Gerald K. Bartley , Darryl J. Becker , John M. Borkenhagen , Paul E. Dahlen , Philip R. Germann , William P. Hovis , Mark O. Maxson
IPC分类号： G06F13/00
CPC分类号： G06F13/1684
摘要： A data communications apparatus includes a central device and a plurality of communication devices. The central device includes a plurality of central port pairs, in which each central port pair includes an input port and an output port. The plurality of communication devices is arranged in a spoke and ring configuration, in which each communication device is part of a communication spoke. Each communication spoke is in communication with a different central port pair. Each communication device is also a part of a communication ring, so that each communication device in a selected communication ring belongs to a different communication spoke.
摘要翻译： 数据通信装置包括中央装置和多个通信装置。 中央设备包括多个中心端口对，其中每个中心端口对包括输入端口和输出端口。 多个通信设备被布置成辐条和环配置，其中每个通信设备是通信辐条的一部分。 每个通话都与不同的中心端口对通信。 每个通信设备也是通信环的一部分，使得所选通信环中的每个通信设备属于不同的通信语音。
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公开(公告)号：US20090031067A1
公开(公告)日：2009-01-29
申请号：US11829250
申请日：2007-07-27
申请人： Gerald K. Bartley , Darryl J. Becker , John M. Borkenhagen , Paul E. Dahlen , Philip R. Germann , William P. Hovis , Mark O. Maxson
发明人： Gerald K. Bartley , Darryl J. Becker , John M. Borkenhagen , Paul E. Dahlen , Philip R. Germann , William P. Hovis , Mark O. Maxson
CPC分类号： G06F13/1684
摘要： A data communications apparatus includes a central device and a plurality of communication devices. The central device includes a plurality of central port pairs, in which each central port pair includes an input port and an output port. The plurality of communication devices is arranged in a spoke and ring configuration, in which each communication device is part of a communication spoke. Each communication spoke is in communication with a different central port pair. Each communication device is also a part of a communication ring, so that each communication device in a selected communication ring belongs to a different communication spoke.
摘要翻译： 数据通信装置包括中央装置和多个通信装置。 中央设备包括多个中心端口对，其中每个中心端口对包括输入端口和输出端口。 多个通信设备被布置成辐条和环配置，其中每个通信设备是通信辐条的一部分。 每个通话都与不同的中心端口对通信。 每个通信设备也是通信环的一部分，使得所选通信环中的每个通信设备属于不同的通信语音。
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3.发明授权Structure and method of implementing power savings during addressing of DRAM architectures 有权在DRAM架构寻址期间实现节能的结构和方法公开(公告)号：US07492662B2
公开(公告)日：2009-02-17
申请号：US11688897
申请日：2007-03-21
申请人： Gerald K. Bartley , Darryl J. Becker , John M. Borkenhagen , Philip R. Germann , William P. Hovis
发明人： Gerald K. Bartley , Darryl J. Becker , John M. Borkenhagen , Philip R. Germann , William P. Hovis
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C7/1012 , G11C7/1051 , G11C7/106 , G11C11/4087 , G11C11/4093 , G11C11/4096
摘要： A random access memory device includes an array of individual memory cells arranged into rows and columns, each memory cell having an access device associated therewith. Each row of the array further includes a plurality of N word lines associated therewith, with a wherein N corresponds to a number of independently accessible partitions of the array, wherein each access device in a given row is coupled to only one of the N word lines of the row. Address decoder logic in signal communication with the array is configured to receive a plurality of row address bits and determine, for a requested row identified by the row address bits, which of the N partitions within the requested row are to be accessed, such that access devices within a selected row, but not within a partition to be accessed, are not activated.
摘要翻译： 随机存取存储器件包括排列成行和列的各个存储器单元的阵列，每个存储器单元具有与其相关联的访问器件。 阵列的每行还包括与其相关联的多个N字线，其中N对应于阵列的独立可访问分区的数量，其中给定行中的每个访问设备仅耦合到N个字线中的一个 的行。 与阵列进行信号通信的地址解码器逻辑被配置为接收多个行地址位，并且对于由行地址位标识的所请求行，确定要请求行中的N个分区中的哪一个被访问， 未被激活的选定行内的设备，但不在要访问的分区内。
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4.发明申请Structure and Method of Implementing Power Savings During Addressing of DRAM Architectures 有权在DRAM架构寻址期间实施节能的结构和方法公开(公告)号：US20080232185A1
公开(公告)日：2008-09-25
申请号：US11688897
申请日：2007-03-21
申请人： Gerald K. Bartley , Darryl J. Becker , John M. Borkenhagen , Philip R. Germann , William P. Hovis
发明人： Gerald K. Bartley , Darryl J. Becker , John M. Borkenhagen , Philip R. Germann , William P. Hovis
CPC分类号： G11C8/10 , G11C7/1012 , G11C7/1051 , G11C7/106 , G11C11/4087 , G11C11/4093 , G11C11/4096
摘要： A random access memory device includes an array of individual memory cells arranged into rows and columns, each memory cell having an access device associated therewith. Each row of the array further includes a plurality of N word lines associated therewith, with a wherein N corresponds to a number of independently accessible partitions of the array, wherein each access device in a given row is coupled to only one of the N word lines of the row. Address decoder logic in signal communication with the array is configured to receive a plurality of row address bits and determine, for a requested row identified by the row address bits, which of the N partitions within the requested row are to be accessed, such that access devices within a selected row, but not within a partition to be accessed, are not activated.
摘要翻译： 随机存取存储器件包括排列成行和列的各个存储器单元的阵列，每个存储器单元具有与其相关联的访问器件。 阵列的每行还包括与其相关联的多个N字线，其中N对应于阵列的独立可访问分区的数量，其中给定行中的每个访问设备仅耦合到N个字线中的一个 的行。 与阵列进行信号通信的地址解码器逻辑被配置为接收多个行地址位，并且对于由行地址位标识的所请求行，确定要请求行中的N个分区中的哪一个被访问， 未被激活的选定行内的设备，但不在要访问的分区内。
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5.发明申请Design Structure Of Implementing Power Savings During Addressing Of DRAM Architectures 有权在DRAM架构寻址期间实现节能的设计结构公开(公告)号：US20090196118A1
公开(公告)日：2009-08-06
申请号：US12024443
申请日：2008-02-01
申请人： Gerald K. Bartley , Darryl J. Becker , John M. Borkenhagen , Philip R. Germann , William P. Hovis
发明人： Gerald K. Bartley , Darryl J. Becker , John M. Borkenhagen , Philip R. Germann , William P. Hovis
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C11/4087
摘要： A design structure embodied in a machine readable medium used in a design process includes random access memory device having an array of individual memory cells arranged into rows and columns, each memory cell having an access device associated therewith. Each row of the array further includes a plurality of N word lines associated therewith, with a wherein N corresponds to a number of independently accessible partitions of the array, wherein each access device in a given row is coupled to only one of the N word lines of the row. Logic in signal communication with the array receives a plurality of row address bits and determine, for a requested row identified by the row address bits, which of the N partitions within the requested row are to be accessed, such that access devices within a selected row, but not within a partition to be accessed, are not activated.
摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构包括具有布置成行和列的各个存储单元的阵列的随机存取存储器件，每个存储单元具有与其相关联的访问设备。 阵列的每行还包括与其相关联的多个N字线，其中N对应于阵列的独立可访问分区的数量，其中给定行中的每个访问设备仅耦合到N个字线中的一个 的行。 与阵列的信号通信中的逻辑接收多个行地址位，并且对于由行地址位标识的请求行，确定要请求的行内的N个分区中的哪一个被访问，使得所选行中的访问设备 ，但不在要访问的分区内，则不会被激活。
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公开(公告)号：US20110238879A1
公开(公告)日：2011-09-29
申请号：US12731320
申请日：2010-03-25
IPC分类号： G06F13/16
CPC分类号： G06F13/1668 , G06F13/161 , Y02D10/14
摘要： Method and apparatus for optimally placing memory devices within a computer system. A memory controller may include circuitry configured to retrieve or one or more performance metrics a plurality of memory devices connected thereto. Based on the performance metrics and one or more predefined rules for placing memory devices, the circuitry may determine an optimal placement of the memory devices in the system.
摘要翻译： 用于最佳地将存储器件放置在计算机系统内的方法和装置。 存储器控制器可以包括被配置为检索连接到其上的多个存储器件的一个或多个性能度量的电路。 基于性能度量和用于放置存储器设备的一个或多个预定义规则，电路可以确定系统中存储器件的最佳布局。
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公开(公告)号：US20080016297A1
公开(公告)日：2008-01-17
申请号：US11457234
申请日：2006-07-13
IPC分类号： G06F13/00
CPC分类号： G06F13/161 , G06F12/08 , G06F12/122
摘要： In a method of controlling computer-readable memory that includes a plurality of memory locations, a usage frequency of a data unit stored in a first memory location is determined. The data unit is moved to a second memory location, different from the first memory location that is selected based on a correspondence between a known latency of the second memory location and the usage frequency of the data unit, in which the second memory location is the primary data storage location for the data unit.
摘要翻译： 在控制包括多个存储器位置的计算机可读存储器的方法中，确定存储在第一存储器位置中的数据单元的使用频率。 数据单元被移动到第二存储器位置，其不同于基于第二存储器位置的已知等待时间与数据单元的使用频率之间的对应关系而选择的第一存储器位置，其中第二存储器位置是 数据单元的主数据存储位置。
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8.发明授权公开(公告)号：US08255628B2
公开(公告)日：2012-08-28
申请号：US12056690
申请日：2008-03-27
IPC分类号： G06F12/00
CPC分类号： G06F13/161
摘要： A design structure for controlling computer-readable memory includes a plurality of memory locations, a usage frequency of a data unit stored in a first memory location is determined. The data unit is moved to a second memory location, different from the first memory location that is selected based on a correspondence between a known latency of the second memory location and the usage frequency of the data unit, in which the second memory location is the primary data storage location for the data unit.
摘要翻译： 用于控制计算机可读存储器的设计结构包括多个存储器位置，确定存储在第一存储器位置中的数据单元的使用频率。 数据单元被移动到第二存储器位置，其不同于基于第二存储器位置的已知等待时间与数据单元的使用频率之间的对应关系而选择的第一存储器位置，其中第二存储器位置是 数据单元的主数据存储位置。
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公开(公告)号：US07707379B2
公开(公告)日：2010-04-27
申请号：US11621182
申请日：2007-01-09
IPC分类号： G06F12/00
CPC分类号： G06F13/161 , G06F12/0802
摘要： In a method of controlling computer-readable memory that includes a plurality of memory locations, a usage frequency of a plurality of data units is determined. Upon each occurrence of a predefined event, a memory latency for each of the plurality of memory locations is determined. After the predefined event, a data unit with a high usage frequency is stored in a memory location with a low latency.
摘要翻译： 在控制包括多个存储器位置的计算机可读存储器的方法中，确定多个数据单元的使用频率。 在每次发生预定事件时，确定多个存储器位置中的每一个的存储器等待时间。 在预定义的事件之后，具有高使用频率的数据单元被存储在具有低延迟的存储器位置中。
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公开(公告)号：US08639879B2
公开(公告)日：2014-01-28
申请号：US12731320
申请日：2010-03-25
IPC分类号： G06F13/00
CPC分类号： G06F13/1668 , G06F13/161 , Y02D10/14
摘要： Method and apparatus for optimally placing memory devices within a computer system. A memory controller may include circuitry configured to retrieve or one or more performance metrics a plurality of memory devices connected thereto. Based on the performance metrics and one or more predefined rules for placing memory devices, the circuitry may determine an optimal placement of the memory devices in the system.
摘要翻译： 用于最佳地将存储器件放置在计算机系统内的方法和装置。 存储器控制器可以包括被配置为检索连接到其上的多个存储器件的一个或多个性能度量的电路。 基于性能度量和用于放置存储器设备的一个或多个预定义规则，电路可以确定系统中存储器件的最佳布局。
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