利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

6 条记录 (耗时 0.023 秒)

    On-Chip Networks for Flexible Three-Dimensional Chip Integration
    2.
    发明申请
    On-Chip Networks for Flexible Three-Dimensional Chip Integration 有权
    用于灵活三维芯片集成的片上网络

    公开(公告)号：US20110119322A1

    公开(公告)日：2011-05-19

    申请号：US12617859

    申请日：2009-11-13

    申请人： Jian Li ,  Steven P. VanderWiel ,  Lixin Zhang

    发明人： Jian Li ,  Steven P. VanderWiel ,  Lixin Zhang

    IPC分类号： G06F15/16

    CPC分类号： G06F15/7842

    摘要： Mechanisms for providing an interconnect layer of a three-dimensional integrated circuit device having multiple independent and cooperative on-chip networks are provided. With regard to an apparatus implementing the interconnect layer, such an apparatus comprises a first integrated circuit layer comprising one or more first functional units and an interconnect layer coupled to the first integrated circuit layer. The first integrated circuit layer and interconnect layer are integrated with one another into a single three-dimensional integrated circuit. The interconnect layer comprises a plurality of independent on-chip communication networks that are independently operable and independently able to be powered on and off, each on-chip communication network comprising a plurality of point-to-point communication links coupled together by a plurality of connection points. The one or more first functional units are coupled to a first independent on-chip communication network of the interconnect layer.

    摘要翻译： 提供具有多个独立和协作的片上网络的具有三维集成电路器件的互连层的机构。 关于实现互连层的装置，这种装置包括包含一个或多个第一功能单元和耦合到第一集成电路层的互连层的第一集成电路层。 第一集成电路层和互连层彼此集成为单个三维集成电路。 互连层包括多个独立的片上通信网络，这些独立的片上通信网络是独立可操作的并且独立地能够通电和关断，每个片上通信网络包括多个点对点通信链路，多个点对点通信链路通过多个 连接点。 一个或多个第一功能单元耦合到互连层的第一独立片上通信网络。

    On-chip networks for flexible three-dimensional chip integration
    4.
    发明授权
    On-chip networks for flexible three-dimensional chip integration 有权
    片上网络为灵活的三维芯片集成

    公开(公告)号：US08386690B2

    公开(公告)日：2013-02-26

    申请号：US12617859

    申请日：2009-11-13

    申请人： Jian Li ,  Steven P. VanderWiel ,  Lixin Zhang

    发明人： Jian Li ,  Steven P. VanderWiel ,  Lixin Zhang

    IPC分类号： G06F13/00 ,  H01L25/00

    CPC分类号： G06F15/7842

    摘要： Mechanisms for providing an interconnect layer of a three-dimensional integrated circuit device having multiple independent and cooperative on-chip networks are provided. With regard to an apparatus implementing the interconnect layer, such an apparatus comprises a first integrated circuit layer comprising one or more first functional units and an interconnect layer coupled to the first integrated circuit layer. The first integrated circuit layer and interconnect layer are integrated with one another into a single three-dimensional integrated circuit. The interconnect layer comprises a plurality of independent on-chip communication networks that are independently operable and independently able to be powered on and off, each on-chip communication network comprising a plurality of point-to-point communication links coupled together by a plurality of connection points. The one or more first functional units are coupled to a first independent on-chip communication network of the interconnect layer.

    摘要翻译： 提供具有多个独立和协作的片上网络的具有三维集成电路器件的互连层的机构。 关于实现互连层的装置，这种装置包括包含一个或多个第一功能单元和耦合到第一集成电路层的互连层的第一集成电路层。 第一集成电路层和互连层彼此集成为单个三维集成电路。 互连层包括多个独立的片上通信网络，这些独立的片上通信网络是独立可操作的并且独立地能够通电和关断，每个片上通信网络包括多个点对点通信链路，多个点对点通信链路通过多个 连接点。 一个或多个第一功能单元耦合到互连层的第一独立片上通信网络。

    Updating a node-based cache LRU tree
    5.
    发明授权
    Updating a node-based cache LRU tree 失效
    更新基于节点的缓存LRU树

    公开(公告)号：US07512739B2

    公开(公告)日：2009-03-31

    申请号：US11428581

    申请日：2006-07-05

    申请人： Aaron C. Sawdey ,  Steven P. VanderWiel

    发明人： Aaron C. Sawdey ,  Steven P. VanderWiel

    IPC分类号： G06F12/00

    CPC分类号： G06F12/123 ,  G06F12/124 ,  Y10S707/99932 ,  Y10S707/99933 ,  Y10S707/99939

    摘要： Exemplary embodiments include a method for updating an Cache LRU tree including: receiving a new cache line; traversing the Cache LRU tree, the Cache LRU tree including a plurality of nodes; biasing a selection the victim line toward those lines with relatively low priorities from the plurality of lines; and replacing a cache line with a relatively low priority with the new cache line.

    摘要翻译： 示例性实施例包括用于更新Cache LRU树的方法，包括：接收新的高速缓存行; 遍历Cache LRU树，包括多个节点的Cache LRU树; 将受害者线路的选择偏向来自多条线路的具有相对较低优先级的线路; 并用新的高速缓存行替换具有较低优先级的高速缓存行。

    A PSEUDO LRU TREE-BASED PRIORITY CACHE
    6.
    发明申请
    A PSEUDO LRU TREE-BASED PRIORITY CACHE 失效
    基于PSEUDO LRU TREE的优先级高速缓存

    公开(公告)号：US20080010415A1

    公开(公告)日：2008-01-10

    申请号：US11428581

    申请日：2006-07-05

    申请人： Aaron C. Sawdey ,  Steven P. VanderWiel

    发明人： Aaron C. Sawdey ,  Steven P. VanderWiel

    IPC分类号： G06F12/00

    CPC分类号： G06F12/123 ,  G06F12/124 ,  Y10S707/99932 ,  Y10S707/99933 ,  Y10S707/99939

    摘要： Exemplary embodiments include a method for updating an Cache LRU tree including: receiving a new cache line; traversing the Cache LRU tree, the Cache LRU tree including a plurality of nodes; biasing a selection the victim line toward those lines with relatively low priorities from the plurality of lines; and replacing a cache line with a relatively low priority with the new cache line.

    摘要翻译： 示例性实施例包括用于更新Cache LRU树的方法，包括：接收新的高速缓存行; 遍历Cache LRU树，包括多个节点的Cache LRU树; 将受害者线路的选择偏向来自多条线路的具有相对较低优先级的线路; 并用新的高速缓存行替换具有较低优先级的高速缓存行。