公开(公告)号：US20060283283A1

公开(公告)日：2006-12-21

申请号：US11314345

申请日：2005-12-22

申请人： Gi Jeong ,  Jae Cha

发明人： Gi Jeong ,  Jae Cha

IPC分类号： G05G5/06

CPC分类号： F16D1/101 ,  B60N2/22 ,  B60N2/933 ,  F16D2001/102 ,  Y10T74/20684

摘要： Disclosed herein is a shaft and hub coupling structure for recliners. The shaft and hub coupling structure of the present invention ensures stable and silent motion of the shaft and the hub, maintains sufficient strength of the shaft, and makes it possible for a process of coupling the shaft to the hub to be easily and correctly conducted.

摘要翻译： 本文公开了一种用于倾斜器的轴和毂联接结构。 本发明的轴和毂联接结构确保轴和轮毂的稳定和无声的运动，保持轴的足够的强度，并且使得可以容易且正确地进行将轴连接到轮毂的过程成为可能。

公开(公告)号：US20070132908A1

公开(公告)日：2007-06-14

申请号：US11584718

申请日：2006-10-19

申请人： Jae Kim ,  Chung Suh ,  Young Chu ,  Jae Cha ,  Jeung Kim

发明人： Jae Kim ,  Chung Suh ,  Young Chu ,  Jae Cha ,  Jeung Kim

IPC分类号： G02F1/1333

CPC分类号： G02F1/133308 ,  G02F2001/133322 ,  G02F2201/465

摘要： The present invention relates to a flat panel display having integral fastening structures for holding the top and bottom chassis. The flat panel display comprises a mold frame enclosing an internal storage space and having a plurality of fastening hooks protruding outward from a side surface thereof; a bottom chassis having a plurality of first coupling openings fastened to the plurality of fastening hooks of the mold frame; and a top chassis having a fastening structure fastened to the bottom chassis, wherein the fastening structure is formed on the area where the mold frame is fastened to the bottom chassis.

摘要翻译： 本发明涉及具有用于保持顶部和底部底盘的整体紧固结构的平板显示器。 平板显示器包括：模制框架，其包围内部存储空间，并且具有从其侧表面向外突出的多个紧固钩; 底部底盘，其具有紧固到所述模具框架的所述多个紧固钩的多个第一联接开口; 以及具有紧固到底部底盘的紧固结构的顶部底盘，其中紧固结构形成在模具框架被紧固到底部底盘的区域上。

公开(公告)号：USD647355S1

公开(公告)日：2011-10-25

申请号：US29360484

申请日：2010-04-27

申请人： Claudio Ponzio ,  Ion Setran ,  Paul Bosveld ,  Vince Voron ,  Jae Cha

设计人： Claudio Ponzio ,  Ion Setran ,  Paul Bosveld ,  Vince Voron ,  Jae Cha

公开(公告)号：US20060181924A1

公开(公告)日：2006-08-17

申请号：US11297052

申请日：2005-12-07

申请人： Jae Cha

发明人： Jae Cha

IPC分类号： G11C16/04

CPC分类号： G11C16/3431 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/105 ,  G11C16/3404

摘要： A non-volatile memory device includes a memory cell array including memory cells, each memory cell being defined at an intersection of a word line and a bit line. A page buffer is coupled to the memory cell array via a sensing line. The page buffer comprises a first latch unit including a first latch circuit and coupled to the sensing line, the first latch unit being configured to be activated during a copy-back program operation to read data stored in a first memory cell and reprogram the data to a second memory cell that is different from the first memory cell. The page buffer also includes a second latch unit including a second latch circuit and coupled to the sensing line, the second latch unit being configured not to be activated during the copy-back operation and be activated during program, read, and verification operations, the second latch unit configured to receive data to be programmed in the memory cells and store the data during the program operation, the second latch unit configured to read the data programmed in the memory cells and store the read data during the read and verification operations.

摘要翻译： 非易失性存储器件包括包括存储器单元的存储单元阵列，每个存储器单元被定义在字线和位线的交叉点处。 页面缓冲器通过感测线耦合到存储单元阵列。 页面缓冲器包括第一锁存单元，其包括第一锁存电路并且耦合到感测线路，第一锁存单元被配置为在复制回程序操作期间被激活以读取存储在第一存储器单元中的数据并将数据重新编程 与第一存储器单元不同的第二存储器单元。 页面缓冲器还包括第二锁存单元，其包括第二锁存电路并且耦合到感测线路，第二锁存单元被配置为在复制操作期间不被激活并且在程序，读取和验证操作期间被激活， 第二锁存单元，被配置为接收要在存储器单元中编程的数据并在编程操作期间存储数据，第二锁存单元被配置为读取在存储器单元中编程的数据并在读取和验证操作期间存储读取的数据。

公开(公告)号：US20060104127A1

公开(公告)日：2006-05-18

申请号：US11122714

申请日：2005-05-05

申请人： Jae Cha ,  Geun Lee

发明人： Jae Cha ,  Geun Lee

IPC分类号： G11C7/10

CPC分类号： G11C7/1006 ,  G11C29/40

摘要： A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data input section; memory cell arrays for storing therein the data which have passed through the data input section; and a data compressor for determining whether or not the data stored in the latch section and the data stored in the memory cell arrays are identical to each other.

公开(公告)号：US20050232033A1

公开(公告)日：2005-10-20

申请号：US10878179

申请日：2004-06-28

申请人： Jae Cha

发明人： Jae Cha

IPC分类号： G11C11/409 ,  G11C7/00 ,  G11C7/10 ,  G11C11/40 ,  G11C11/407

CPC分类号： G11C7/1087 ,  G11C7/1078 ,  G11C7/1093

摘要： Provided is directed to a data input apparatus and a method of DDR SDRAM which can improve reliability of a circuit operation by transferring data inputted after applying a data strobe signal DQS to an input/output bus GIO by a exact timing, by means of correctly arranging the data strobe signal DQS and a data input strobe pulse dinstbp regardless of time difference of inputting the data strobe signal DQS after a write command, in response to generating a data input strobe pulse dinstbp used to load data to the input/output bus GIO as a data strobe pulse dsp identical to the data strobe signal DQS.

摘要翻译： 本发明涉及一种DDR SDRAM的数据输入装置和方法，其可以通过将精确定时将数据选通信号DQS输入的数据传送到输入/输出总线GIO，从而提高电路操作的可靠性，借助于正确布置 数据选通信号DQS和数据输入选通脉冲dinstbp，而不管在写命令之后输入数据选通信号DQS的时间差，响应于产生用于将数据加载到输入/输出总线GIO的数据输入选通脉冲dinstbp，作为 与数据选通信号DQS相同的数据选通脉冲dsp。