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    Charge pump phase locked loop with improved power supply rejection
    2.
    发明授权
    Charge pump phase locked loop with improved power supply rejection 有权
    充电泵锁相环，具有改进的电源抑制

    公开(公告)号：US06963233B2

    公开(公告)日：2005-11-08

    申请号：US10793367

    申请日：2004-03-03

    申请人： Gianni Puccio ,  Biagio Bisanti ,  Stefano Cipriani

    发明人： Gianni Puccio ,  Biagio Bisanti ,  Stefano Cipriani

    IPC分类号： H03L7/00 ,  H03L7/06 ,  H03L7/089 ,  H03L7/18

    CPC分类号： H03L7/0895 ,  H03L7/18

    摘要： A phase lock loop circuit (60) has a phase frequency detector (62), a charge pump (64), an active filter (87) and a voltage-controlled oscillator (100). The phase detector generates signals responsive to reference signal FR and VCO output signal FV. A charge pump generates a voltage at the input of a first transmission gate (76) according to the values of the phase detector signals. A predetermined voltage is generated at the input of a second transmission gate (112). When the transmission gates (76, 110) are closed (low impedance) the charge pump may sink or source current to the inverting input of the operational amplifier (86) of the active filter 86 and the predetermined voltage is applied to the non-inverting input. When the transmission gates are open (high impedance state) the inverting input is electrically isolated from the node and the non-inverting output is isolated from the power supply.

    摘要翻译： 锁相环电路（60）具有相位频率检测器（62），电荷泵（64），有源滤波器（87）和压控振荡器（100）。 相位检测器响应于参考信号F SUB和VCO输出信号F OUT产生信号。 电荷泵根据相位检测器信号的值在第一传输门（76）的输入端产生电压。 在第二传输门（112）的输入处产生预定电压。 当传输门（76,110）闭合（低阻抗）时，电荷泵可以将有源滤波器86的运算放大器（86）的反相输入端的电流吸收或输出，并将预定的电压施加到非反相 输入。 当传输门打开（高阻抗状态）时，反相输入与节点电隔离，非反相输出与电源隔离。

    CHARGE PUMP PHASE LOCKED LOOP WITH IMPROVED POWER SUPPLY REJECTION
    6.
    发明申请
    CHARGE PUMP PHASE LOCKED LOOP WITH IMPROVED POWER SUPPLY REJECTION 有权
    充电泵相位锁定环与改进的电源抑制

    公开(公告)号：US20050195002A1

    公开(公告)日：2005-09-08

    申请号：US10793367

    申请日：2004-03-03

    申请人： Gianni Puccio ,  Biagio Bisanti ,  Stefano Cipriani

    发明人： Gianni Puccio ,  Biagio Bisanti ,  Stefano Cipriani

    IPC分类号： H03L7/00 ,  H03L7/06 ,  H03L7/089 ,  H03L7/18

    CPC分类号： H03L7/0895 ,  H03L7/18

    摘要： A phase lock loop circuit (60) has a phase frequency detector (62), a charge pump (64), an active filter (87) and a voltage-controlled oscillator (100). The phase detector generates signals responsive to reference signal FR and VCO output signal FV. A charge pump generates a voltage at the input of a first transmission gate (76) according to the values of the phase detector signals. A predetermined voltage is generated at the input of a second transmission gate (112). When the transmission gates (76, 110) are closed (low impedance) the charge pump may sink or source current to the inverting input of the operational amplifier (86) of the active filter 86 and the predetermined voltage is applied to the non-inverting input. When the transmission gates are open (high impedance state) the inverting input is electrically isolated from the node and the non-inverting output is isolated from the power supply.

    摘要翻译： 锁相环电路（60）具有相位频率检测器（62），电荷泵（64），有源滤波器（87）和压控振荡器（100）。 相位检测器响应于参考信号F SUB和VCO输出信号F OUT产生信号。 电荷泵根据相位检测器信号的值在第一传输门（76）的输入端产生电压。 在第二传输门（112）的输入处产生预定电压。 当传输门（76,110）关闭（低阻抗）时，电荷泵可以将有源滤波器86的运算放大器（86）的反相输入端的电流吸收或输出，并将预定的电压施加到非反相 输入。 当传输门打开（高阻抗状态）时，反相输入与节点电隔离，非反相输出与电源隔离。

    Charge pump phase locked loop
    9.
    发明授权
    Charge pump phase locked loop 有权
    电荷泵锁相环

    公开(公告)号：US07158600B2

    公开(公告)日：2007-01-02

    申请号：US10154684

    申请日：2002-05-24

    申请人： Gianni Puccio ,  Biagio Bisanti ,  Stefano Cipriani

    发明人： Gianni Puccio ,  Biagio Bisanti ,  Stefano Cipriani

    IPC分类号： H03D3/24

    CPC分类号： H03L7/0895

    摘要： A phase lock loop circuit 60 has a phase frequency detector 62, a charge pump 64, an active filter 87 and a voltage-controlled oscillator 100. The phase detector generates UP and DN signals indicative of the relative frequency of FR, a reference signal, and FV, a signal controlled by the voltage-controlled oscillator. A charge pump using logic gates (buffer 66 and inverter 68) to produce a voltage drop over resistors 74 and 84 to generate a voltage at a node coupled to the input of transmission gate 76 according to the values of the UP and DN signals. When the transmission gate 76 is closed (low impedance) the charge pump may sink or source current to the inverting input of the operational amplifier 86 of the active filter 86. When the transmission gate is open (high impedance state) the inverting input is electrically isolated from the node.

    摘要翻译： 锁相环电路60具有相位频率检测器62，电荷泵64，有源滤波器87和压控振荡器100。 相位检测器产生指示由压控振荡器控制的信号的F SUB相对频率，参考信号和F OUT的UP信号和DN信号。 使用逻辑门（缓冲器66和反相器68）的电荷泵，以在电阻器74和84上产生电压降，以根据UP和DN信号的值在耦合到传输门76的输入端的节点处产生电压。 当传输门76闭合（低阻抗）时，电荷泵可以将电流吸收或馈送到有源滤波器86的运算放大器86的反相输入端。 当传输门打开（高阻抗状态）时，反相输入与节点电隔离。

    Radio frequency modulator
    10.
    发明授权
    Radio frequency modulator 有权
    射频调制器

    公开(公告)号：US07136626B2

    公开(公告)日：2006-11-14

    申请号：US10071919

    申请日：2002-02-08

    申请人： Biagio Bisanti ,  Stefano Cipriani ,  Eric Duvivier

    发明人： Biagio Bisanti ,  Stefano Cipriani ,  Eric Duvivier

    IPC分类号： H04B1/02 ,  H04B1/04

    CPC分类号： H03C3/0983 ,  H03C3/0966

    摘要： A transmitter architecture (200) provides for a stable and low noise modulator where the modulation bandwidth is uncorrelated to the TX loop bandwidth. The output signal (228) of the TX loop is demodulated by a demodulator (208) and the demodulated signal is compared by a comparator (206) with the modulating input signal (202). The output of the comparator is then used to adjust a digital pre-emphasis filter (204) which preconditions the modulating input signal (202) in the digital domain. The preconditioning approach of the present invention provides for low noise because the transmitter designer can chose a narrow band for the TX loop which will also filter out the noise coming from the additional synthesizer (226) used to down convert the input signal.

    摘要翻译： 发射机架构（200）提供稳定和低噪声调制器，其中调制带宽与TX环路带宽不相关。 TX环路的输出信号（228）由解调器（208）解调，并且解调信号由比较器（206）与调制输入信号（202）进行比较。 然后比较器的输出用于调整预编码数字域中的调制输入信号（202）的数字预加重滤波器（204）。 本发明的预处理方法提供低噪声，因为发射机设计者可以为TX环路选择窄带，其也将滤除来自用于下变频输入信号的附加合成器（226）的噪声。