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公开(公告)号：US07318181B2
公开(公告)日：2008-01-08
申请号：US11166500
申请日：2005-06-24
IPC分类号： G11C29/00
CPC分类号： G11C29/12015 , G11C16/04 , G11C29/16 , G11C29/48 , G11C29/50004
摘要： A circuit to monitor the activity of a memory device during program/erase operations that are managed by a ROM-based microcontroller. Different signals can be monitored according to different test modes. The ROM-based microcontroller is triggered by a clock that can be connected to an internal fixed frequency oscillator or to an external clock source for which the frequency can be varied from 0 Hz to any frequency required by the application. The circuit outputs state machine status data, read only memory addresses, and memory status information in a series of multiplexing operations to provide a tester with the ability to determine the state of a memory device during various memory operations.
摘要翻译： 用于在由基于ROM的微控制器管理的编程/擦除操作期间监视存储器件的活动的电路。 可以根据不同的测试模式监控不同的信号。 基于ROM的微控制器由可连接到内部固定频率振荡器或外部时钟源的时钟触发，频率可以从0 Hz变化到应用所需的任何频率。 电路在一系列复用操作中输出状态机状态数据，只读存储器地址和存储器状态信息，以向测试者提供在各种存储器操作期间确定存储器件的状态的能力。
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公开(公告)号：US06977852B2
公开(公告)日：2005-12-20
申请号：US10696973
申请日：2003-10-30
IPC分类号： G01R31/28 , G06F9/00 , G06F9/24 , G06F11/00 , G06F15/177 , G11C7/00 , G11C17/00 , G11C29/16 , G11C29/48
CPC分类号： G11C29/12015 , G11C16/04 , G11C29/16 , G11C29/48 , G11C29/50004
摘要： A circuit to monitor the activity of a memory device during program/erase operations that are managed by a ROM-based microcontroller. Different signals can be monitored according to different test modes. The ROM-based microcontroller is triggered by a clock that can be connected to an internal fixed frequency oscillator or to an external clock source for which the frequency can be varied from 0 Hz to any frequency required by the application. The circuit outputs state machine status data, read only memory addresses, and memory status information in a series of multiplexing operations to provide a tester with the ability to determine the state of a memory device during various memory operations.
摘要翻译： 用于在由基于ROM的微控制器管理的编程/擦除操作期间监视存储器件的活动的电路。 可以根据不同的测试模式监控不同的信号。 基于ROM的微控制器由可连接到内部固定频率振荡器或外部时钟源的时钟触发，频率可以从0 Hz变化到应用所需的任何频率。 电路在一系列复用操作中输出状态机状态数据，只读存储器地址和存储器状态信息，以向测试者提供在各种存储器操作期间确定存储器件的状态的能力。
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公开(公告)号：US20050240851A1
公开(公告)日：2005-10-27
申请号：US11166500
申请日：2005-06-24
IPC分类号： G01R31/28 , G06F9/00 , G06F9/24 , G06F11/00 , G06F15/177 , G11C7/00 , G11C17/00 , G11C29/16 , G11C29/48
CPC分类号： G11C29/12015 , G11C16/04 , G11C29/16 , G11C29/48 , G11C29/50004
摘要： A circuit to monitor the activity of a memory device during program/erase operations that are managed by a ROM-based microcontroller. Different signals can be monitored according to different test modes. The ROM-based microcontroller is triggered by a clock that can be connected to an internal fixed frequency oscillator or to an external clock source for which the frequency can be varied from 0 Hz to any frequency required by the application. The circuit outputs state machine status data, read only memory addresses, and memory status information in a series of multiplexing operations to provide a tester with the ability to determine the state of a memory device during various memory operations.
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公开(公告)号：US20100174855A1
公开(公告)日：2010-07-08
申请号：US12651827
申请日：2010-01-04
申请人： Luca De Santis , Pasquale Conenna
发明人： Luca De Santis , Pasquale Conenna
CPC分类号： G06F12/0246 , G06F12/0875 , G06F13/16 , G06F13/1694 , G06F2212/202 , G06F2212/452 , G11C16/10
摘要： A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core of the memory device for controlling operation of the analog/memory core. The analog/memory core has an array of flash memory cells and supporting analog access circuitry. A bus controller is coupled to the register bank. The bus controller is adapted to receive a second signal from the register bank and to send a third signal to the register bank for updating the register bank. A select register is coupled to the register bank. A processor is coupled to the bus controller and the select register.
摘要翻译： 提供了一种用于存储器件和方法的控制器。 控制器具有可更新的寄存器组，其适于将第一信号发送到存储器件的模拟/存储器核心，以控制模拟/存储器核心的操作。 模拟/存储器内核具有闪存单元阵列和支持模拟存取电路。 总线控制器耦合到寄存器组。 总线控制器适于从寄存器组接收第二信号，并向寄存器组发送第三信号以更新寄存器组。 选择寄存器耦合到寄存器组。 一个处理器耦合到总线控制器和选择寄存器。
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公开(公告)号：US07644240B2
公开(公告)日：2010-01-05
申请号：US11489778
申请日：2006-07-20
申请人： Luca De Santis , Pasquale Conenna
发明人： Luca De Santis , Pasquale Conenna
CPC分类号： G06F12/0246 , G06F12/0875 , G06F13/16 , G06F13/1694 , G06F2212/202 , G06F2212/452 , G11C16/10
摘要： A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core of the memory device for controlling operation of the analog/memory core. The analog/memory core has an array of flash memory cells and supporting analog access circuitry. A bus controller is coupled to the register bank. The bus controller is adapted to receive a second signal from the register bank and to send a third signal to the register bank for updating the register bank. A select register is coupled to the register bank. A processor is coupled to the bus controller and the select register.
摘要翻译： 提供了一种用于存储器件和方法的控制器。 控制器具有可更新的寄存器组，其适于将第一信号发送到存储器件的模拟/存储器核心，以控制模拟/存储器核心的操作。 模拟/存储器内核具有闪存单元阵列和支持模拟存取电路。 总线控制器耦合到寄存器组。 总线控制器适于从寄存器组接收第二信号，并向寄存器组发送第三信号以更新寄存器组。 选择寄存器耦合到寄存器组。 处理器耦合到总线控制器和选择寄存器。
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公开(公告)号：US07587560B2
公开(公告)日：2009-09-08
申请号：US11489904
申请日：2006-07-20
申请人： Luca De Santis , Pasquale Conenna
发明人： Luca De Santis , Pasquale Conenna
CPC分类号： G06F12/0246 , G06F12/0875 , G06F13/16 , G06F13/1694 , G06F2212/202 , G06F2212/452 , G11C16/10
摘要： A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core of the memory device for controlling operation of the analog/memory core. The analog/memory core has an array of flash memory cells and supporting analog access circuitry. A bus controller is coupled to the register bank. The bus controller is adapted to receive a second signal from the register bank and to send a third signal to the register bank for updating the register bank. A select register is coupled to the register bank. A processor is coupled to the bus controller and the select register.
摘要翻译： 提供了一种用于存储器件和方法的控制器。 控制器具有可更新的寄存器组，其适于将第一信号发送到存储器件的模拟/存储器核心，以控制模拟/存储器核心的操作。 模拟/存储器内核具有闪存单元阵列和支持模拟存取电路。 总线控制器耦合到寄存器组。 总线控制器适于从寄存器组接收第二信号，并向寄存器组发送第三信号以更新寄存器组。 选择寄存器耦合到寄存器组。 处理器耦合到总线控制器和选择寄存器。
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公开(公告)号：US20060259714A1
公开(公告)日：2006-11-16
申请号：US11489904
申请日：2006-07-20
申请人： Luca De Santis , Pasquale Conenna
发明人： Luca De Santis , Pasquale Conenna
IPC分类号： G06F13/00
CPC分类号： G06F12/0246 , G06F12/0875 , G06F13/16 , G06F13/1694 , G06F2212/202 , G06F2212/452 , G11C16/10
摘要： A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core of the memory device for controlling operation of the analog/memory core. The analog/memory core has an array of flash memory cells and supporting analog access circuitry. A bus controller is coupled to the register bank. The bus controller is adapted to receive a second signal from the register bank and to send a third signal to the register bank for updating the register bank. A select register is coupled to the register bank. A processor is coupled to the bus controller and the select register.
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公开(公告)号：US20060259713A1
公开(公告)日：2006-11-16
申请号：US11489778
申请日：2006-07-20
申请人： Luca De Santis , Pasquale Conenna
发明人： Luca De Santis , Pasquale Conenna
IPC分类号： G06F13/00
CPC分类号： G06F12/0246 , G06F12/0875 , G06F13/16 , G06F13/1694 , G06F2212/202 , G06F2212/452 , G11C16/10
摘要： A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core of the memory device for controlling operation of the analog/memory core. The analog/memory core has an array of flash memory cells and supporting analog access circuitry. A bus controller is coupled to the register bank. The bus controller is adapted to receive a second signal from the register bank and to send a third signal to the register bank for updating the register bank. A select register is coupled to the register bank. A processor is coupled to the bus controller and the select register.
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公开(公告)号：US08667232B2
公开(公告)日：2014-03-04
申请号：US12651827
申请日：2010-01-04
申请人： Luca De Santis , Pasquale Conenna
发明人： Luca De Santis , Pasquale Conenna
CPC分类号： G06F12/0246 , G06F12/0875 , G06F13/16 , G06F13/1694 , G06F2212/202 , G06F2212/452 , G11C16/10
摘要： A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core of the memory device for controlling operation of the analog/memory core. The analog/memory core has an array of flash memory cells and supporting analog access circuitry. A bus controller is coupled to the register bank. The bus controller is adapted to receive a second signal from the register bank and to send a third signal to the register bank for updating the register bank. A select register is coupled to the register bank. A processor is coupled to the bus controller and the select register.
摘要翻译： 提供了一种用于存储器件和方法的控制器。 控制器具有可更新的寄存器组，其适于将第一信号发送到存储器件的模拟/存储器核心，以控制模拟/存储器核心的操作。 模拟/存储器内核具有闪存单元阵列和支持模拟存取电路。 总线控制器耦合到寄存器组。 总线控制器适于从寄存器组接收第二信号，并向寄存器组发送第三信号以更新寄存器组。 选择寄存器耦合到寄存器组。 处理器耦合到总线控制器和选择寄存器。
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公开(公告)号：US07272683B2
公开(公告)日：2007-09-18
申请号：US10722110
申请日：2003-11-25
申请人： Luca De Santis , Pasquale Conenna
发明人： Luca De Santis , Pasquale Conenna
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0875 , G06F13/16 , G06F13/1694 , G06F2212/202 , G06F2212/452 , G11C16/10
摘要： A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core of the memory device for controlling operation of the analog/memory core. The analog/memory core has an array of flash memory cells and supporting analog access circuitry. A bus controller is coupled to the register bank. The bus controller is adapted to receive a second signal from the register bank and to send a third signal to the register bank for updating the register bank. A select register is coupled to the register bank. A processor is coupled to the bus controller and the select register.
摘要翻译： 提供了一种用于存储器件和方法的控制器。 控制器具有可更新的寄存器组，其适于向存储器件的模拟/存储器核发送第一信号，以控制模拟/存储器核的操作。 模拟/存储器内核具有闪存单元阵列和支持模拟存取电路。 总线控制器耦合到寄存器组。 总线控制器适于从寄存器组接收第二信号，并向寄存器组发送第三信号以更新寄存器组。 选择寄存器耦合到寄存器组。 处理器耦合到总线控制器和选择寄存器。
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