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公开(公告)号：US07164607B2
公开(公告)日：2007-01-16
申请号：US11142114
申请日：2005-06-01
IPC分类号： G11C7/10
CPC分类号： G11C7/106 , G11C7/1021 , G11C7/103 , G11C7/1051 , G11C7/1066
摘要： Methods and apparatus for a memory device including a burst architecture employ a double bus architecture that is multiplexed onto an output bus. The resulting architecture effectively facilitates doubling throughput without increasing memory device latency.
摘要翻译： 包括突发体系结构的存储器件的方法和装置采用复用到输出总线上的双总线架构。 所产生的架构有效地增加了吞吐量，而不会增加内存设备的延迟。
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公开(公告)号：US07565587B2
公开(公告)日：2009-07-21
申请号：US11519415
申请日：2006-09-12
IPC分类号： G11C29/00
CPC分类号： G11C16/3445 , G11C16/344
摘要： Memory devices and methods of operating memory devices provide for using differing potentials during erase verify operations facilitate normal erase operations and subsequent erase check operations. Such apparatus and methods facilitate subsequent checks for data gain of erased memory cells using abbreviated procedures compared to normal erase operations.
摘要翻译： 操作存储器件的存储器件和方法在擦除验证操作期间提供使用不同的电位，便于正常擦除操作和随后的擦除检查操作。 与普通擦除操作相比，这种装置和方法便于使用缩写的过程随后检查擦除的存储器单元的数据增益。
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公开(公告)号：US06917545B2
公开(公告)日：2005-07-12
申请号：US10367587
申请日：2003-02-14
CPC分类号： G11C7/106 , G11C7/1021 , G11C7/103 , G11C7/1051 , G11C7/1066
摘要： A method and apparatus for a memory device including a burst architecture employs a double bus architecture that is multiplexed onto an output bus at clock rate that is doubled. The resulting architecture effectively doubles throughput without increasing memory device latency.
摘要翻译： 包括突发体系结构的存储器件的方法和装置采用双总线结构，其双倍的时钟速率复用到输出总线上。 所产生的架构有效地增加了吞吐量，而不会增加内存设备的延迟。
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公开(公告)号：US07117402B2
公开(公告)日：2006-10-03
申请号：US10286450
申请日：2002-11-01
IPC分类号： G01R31/28
CPC分类号： G11C16/3445 , G11C16/344
摘要： A flash memory erase check circuit is disclosed. One embodiment includes an on-chip circuit that quickly and reliably checks that the flash memory chip is actually erased even after data gain that has resulted, for example, from a long period of storage.
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公开(公告)号：US20100138623A1
公开(公告)日：2010-06-03
申请号：US11795358
申请日：2007-05-10
IPC分类号： G06F12/14
摘要： In one embodiment, a non-volatile memory device includes a plurality of protection bits denoting that an area of memory in the device must be protected from being erased or programmed. The memory device further includes a majority logic circuit for determining the logic state of the majority of the plurality of protection bits. Another embodiment includes a pattern generator for generating the logic levels to be stored in the plurality of protection bits.
摘要翻译： 在一个实施例中，非易失性存储器件包括多个保护位，其表示必须保护器件中的存储器区域不被擦除或编程。 存储器件还包括用于确定多个保护位中大部分的逻辑状态的多数逻辑电路。 另一个实施例包括用于产生要存储在多个保护位中的逻辑电平的模式发生器。
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公开(公告)号：US07154800B2
公开(公告)日：2006-12-26
申请号：US11196913
申请日：2005-08-04
IPC分类号： G11C17/18
CPC分类号： G11C16/26 , G11C29/789
摘要： The fuse and latch circuit has a Floating gate Avalanche injection Metal Oxide Semiconductor (FAMOS) transistor (fuse) that is coupled to a read circuit. The read circuit includes circuitry that reduces the drive strength of the fuse. A transmission gate couples the read circuit to the latch circuit. The transmission gate isolates the fuse from the latch. When a reset condition occurs, the data that was in latch circuit remains after the reset condition is complete.
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公开(公告)号：US09406388B2
公开(公告)日：2016-08-02
申请号：US11795358
申请日：2007-05-10
摘要： In one embodiment, a non-volatile memory device includes a plurality of protection bits denoting that an area of memory in the device must be protected from being erased or programmed. The memory device further includes a majority logic circuit for determining the logic state of the majority of the plurality of protection bits. Another embodiment includes a pattern generator for generating the logic levels to be stored in the plurality of protection bits.
摘要翻译： 在一个实施例中，非易失性存储器件包括多个保护位，其表示必须保护器件中的存储器区域不被擦除或编程。 存储器件还包括用于确定多个保护位中大部分的逻辑状态的多数逻辑电路。 另一个实施例包括用于产生要存储在多个保护位中的逻辑电平的模式发生器。
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公开(公告)号：US20080195795A1
公开(公告)日：2008-08-14
申请号：US12107296
申请日：2008-04-22
IPC分类号： G06F12/00
CPC分类号： G11C7/1021 , G11C7/1039
摘要： A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to minimize latency which would otherwise occur in multichannel operation.
摘要翻译： 用于多通道连续或固定突发模式操作的存储器件包括多个脉冲串地址计数器电路和相关联的控制逻辑，以最小化否则将在多通道操作中发生的等待时间。
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公开(公告)号：US07263022B2
公开(公告)日：2007-08-28
申请号：US11472670
申请日：2006-06-22
IPC分类号： G11C17/18
CPC分类号： G11C16/26 , G11C29/789
摘要： The fuse and latch circuit has a Floating gate Avalanche injection Metal Oxide Semiconductor (FAMOS) transistor (fuse) that is coupled to a read circuit. The read circuit includes circuitry that reduces the drive strength of the fuse. A transmission gate couples the read circuit to the latch circuit. The transmission gate isolates the fuse from the latch. When a reset condition occurs, the data that was in latch circuit remains after the reset condition is complete.
摘要翻译： 保险丝和锁存电路具有耦合到读取电路的浮动门雪崩注入金属氧化物半导体（FAMOS）晶体管（保险丝）。 读取电路包括降低保险丝的驱动强度的电路。 传输门将读取电路耦合到锁存电路。 传输门将保险丝与锁存器隔离。 当复位条件发生时，复位条件完成后，锁存电路中的数据保持不变。
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公开(公告)号：US07363452B2
公开(公告)日：2008-04-22
申请号：US11343818
申请日：2006-01-31
IPC分类号： G06F12/00
CPC分类号： G11C7/1021 , G11C7/1039
摘要： A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to minimize latency which would otherwise occur in multichannel operation.
摘要翻译： 用于多通道连续或固定突发模式操作的存储器件包括多个脉冲串地址计数器电路和相关联的控制逻辑，以最小化否则将在多通道操作中发生的等待时间。
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