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    Structure and method for thermally stressing or testing a semiconductor device
    1.
    发明授权
    Structure and method for thermally stressing or testing a semiconductor device 有权
    用于热应力或测试半导体器件的结构和方法

    公开(公告)号：US07375371B2

    公开(公告)日：2008-05-20

    申请号：US11307324

    申请日：2006-02-01

    申请人： Giuseppe La Rosa ,  Kevin W. Kolvenbach ,  John Greg Massey ,  Ping-Chuan Wang ,  Kai Xiu

    发明人： Giuseppe La Rosa ,  Kevin W. Kolvenbach ,  John Greg Massey ,  Ping-Chuan Wang ,  Kai Xiu

    IPC分类号： H01L23/58 ,  H01L29/10 ,  G01R31/02

    CPC分类号： G01R31/2856

    摘要： A structure is provided which includes at least one semiconductor device and a diffusion heater in a continuous active semiconductor area of a substrate. One or more semiconductor devices are provided in a first region of the active semiconductor area and a diffusion heater is disposed adjacent thereto which consists essentially of a semiconductor material included in the active semiconductor area. Conductive isolation between the first region and the diffusion heater is achieved through use of a separating gate. The separating gate overlies an intermediate region of the active semiconductor area between the first region and the diffusion heater and the separating gate is biasable to conductively isolate the first region from the diffusion heater.

    摘要翻译： 提供了一种在衬底的连续有源半导体区域中包括至少一个半导体器件和扩散加热器的结构。 一个或多个半导体器件设置在有源半导体区域的第一区域中，并且扩散加热器邻近设置，其主要由包含在有源半导体区域中的半导体材料组成。 通过使用分离栅极实现第一区域和扩散加热器之间的导电隔离。 分离栅极覆盖在第一区域和扩散加热器之间的有源半导体区域的中间区域，并且分离栅极可偏置以将第一区域与扩散加热器导电隔离。

    STRUCTURE AND METHOD FOR THERMALLY STRESSING OR TESTING A SEMICONDUCTOR DEVICE
    2.
    发明申请
    STRUCTURE AND METHOD FOR THERMALLY STRESSING OR TESTING A SEMICONDUCTOR DEVICE 有权
    用于热应力或测试半导体器件的结构和方法

    公开(公告)号：US20070235769A1

    公开(公告)日：2007-10-11

    申请号：US11307324

    申请日：2006-02-01

    申请人： Giuseppe La Rosa ,  Kevin Kolvenbach ,  John Massey ,  Ping-Chuan Wang ,  Kai Xiu

    发明人： Giuseppe La Rosa ,  Kevin Kolvenbach ,  John Massey ,  Ping-Chuan Wang ,  Kai Xiu

    IPC分类号： H01L29/76

    CPC分类号： G01R31/2856

    摘要： A structure is provided which includes at least one semiconductor device and a diffusion heater in a continuous active semiconductor area of a substrate. One or more semiconductor devices are provided in a first region of the active semiconductor area and a diffusion heater is disposed adjacent thereto which consists essentially of a semiconductor material included in the active semiconductor area. Conductive isolation between the first region and the diffusion heater is achieved through use of a separating gate. The separating gate overlies an intermediate region of the active semiconductor area between the first region and the diffusion heater and the separating gate is biasable to conductively isolate the first region from the diffusion heater.

    摘要翻译： 提供了一种在衬底的连续有源半导体区域中包括至少一个半导体器件和扩散加热器的结构。 一个或多个半导体器件设置在有源半导体区域的第一区域中，并且扩散加热器邻近设置，其主要由包含在有源半导体区域中的半导体材料组成。 通过使用分离栅极实现第一区域和扩散加热器之间的导电隔离。 分离栅极覆盖在第一区域和扩散加热器之间的有源半导体区域的中间区域，并且分离栅极可偏置以将第一区域与扩散加热器导电隔离。

    METHOD AND APPARATUS FOR DYNAMIC CHARACTERIZATION OF RELIABILITY WEAROUT MECHANISMS
    3.
    发明申请
    METHOD AND APPARATUS FOR DYNAMIC CHARACTERIZATION OF RELIABILITY WEAROUT MECHANISMS 失效
    用于动态表征可靠性磨损机制的方法和装置

    公开(公告)号：US20090167336A1

    公开(公告)日：2009-07-02

    申请号：US11968444

    申请日：2008-01-02

    申请人： Giuseppe La Rosa ,  Kevin Kolvenbach ,  Ping-Chuan Wang ,  Stephen D. Wyatt

    发明人： Giuseppe La Rosa ,  Kevin Kolvenbach ,  Ping-Chuan Wang ,  Stephen D. Wyatt

    IPC分类号： G01R31/02

    CPC分类号： G01R31/2858 ,  G01R31/2856

    摘要： A method and apparatus for dynamic characterization of reliability wearout mechanisms is disclosed. The system comprises an integrated circuit incorporating a device under test to be measured, structure for inputting a waveform to the device under test for a first predetermined time interval, structure for disabling the inputting of the waveform to the device under test, structure for measuring one or more fundamental parameters of the device under test after a second predetermined time interval, and structure for calculating an aging estimate of the device under test without the influence of recovery effect based on the one or more measured fundamental parameters. The time between stressing and measurement is precisely controlled, providing for repeatable experiments, and serves to minimize measurement error caused by recovery effects.

    摘要翻译： 公开了用于动态表征可靠性损耗机制的方法和装置。 该系统包括结合被测器件的集成电路，用于以第一预定时间间隔向待测器件输入波形的结构，用于禁止向被测器件输入波形的结构，用于测量一个 或更多的基本参数，以及在不受基于一个或多个测量的基本参数的恢复效果的影响下计算被测设备的老化估计的结构。 压力和测量之间的时间被精确控制，提供可重复的实验，并且用于最小化由恢复效果引起的测量误差。

    STRUCTURE AND METHODOLOGY FOR CHARACTERIZING DEVICE SELF-HEATING
    4.
    发明申请
    STRUCTURE AND METHODOLOGY FOR CHARACTERIZING DEVICE SELF-HEATING 失效
    用于表征装置自加热的结构和方法

    公开(公告)号：US20080112458A1

    公开(公告)日：2008-05-15

    申请号：US11559120

    申请日：2006-11-13

    申请人： Ping-Chuan Wang ,  Paul A. Hyde ,  Kevin Kolvenbach ,  Giuseppe La Rosa

    发明人： Ping-Chuan Wang ,  Paul A. Hyde ,  Kevin Kolvenbach ,  Giuseppe La Rosa

    IPC分类号： G01N25/20

    CPC分类号： G01N25/18

    摘要： A method comprises determining a poly-gate temperature for a given device and determining channel temperatures of monitor devices. The method further includes extrapolating channel temperatures of the monitor devices to obtain a channel temperature for the given device. The difference in temperature (ΔT value) is determined for the given device based on the poly-gate temperature and the channel temperature. A device comprises a heating device having a poly gate with at least one contact at each end thereof and a plurality of monitor device spaced at known distances from the heating device

    摘要翻译： 一种方法包括确定给定装置的多栅极温度并确定监测装置的通道温度。 该方法还包括外推监测装置的通道温度以获得给定装置的通道温度。 基于多栅极温度和通道温度，为给定器件确定温度差（DeltaT值）。 一种装置包括加热装置，该加热装置具有在其两端具有至少一个触点的多晶硅栅极以及与加热装置隔开已知距离的多个监测装置

    Structure and methodology for characterizing device self-heating
    5.
    发明授权
    Structure and methodology for characterizing device self-heating 失效
    表征设备自热的结构和方法

    公开(公告)号：US07805274B2

    公开(公告)日：2010-09-28

    申请号：US11559120

    申请日：2006-11-13

    申请人： Ping-Chuan Wang ,  Paul A. Hyde ,  Kevin Kolvenbach ,  Giuseppe La Rosa

    发明人： Ping-Chuan Wang ,  Paul A. Hyde ,  Kevin Kolvenbach ,  Giuseppe La Rosa

    IPC分类号： G01N25/20

    CPC分类号： G01N25/18

    摘要： A method comprises determining a poly-gate temperature for a given device and determining channel temperatures of monitor devices. The method further includes extrapolating channel temperatures of the monitor devices to obtain a channel temperature for the given device. The difference in temperature (ΔT value) is determined for the given device based on the poly-gate temperature and the channel temperature. A device comprises a heating device having a poly gate with at least one contact at each end thereof and a plurality of monitor device spaced at known distances from the heating device

    摘要翻译： 一种方法包括确定给定装置的多栅极温度并确定监测装置的通道温度。 该方法还包括外推监视器装置的通道温度以获得给定装置的通道温度。 基于多栅极温度和通道温度，为给定器件确定温度差（＆Dgr; T值）。 一种装置包括加热装置，该加热装置具有在其两端具有至少一个触点的多晶硅栅极以及与加热装置隔开已知距离的多个监测装置

    Method and apparatus for dynamic characterization of reliability wearout mechanisms
    6.
    发明授权
    Method and apparatus for dynamic characterization of reliability wearout mechanisms 失效
    用于动态表征可靠性损耗机制的方法和装置

    公开(公告)号：US07710141B2

    公开(公告)日：2010-05-04

    申请号：US11968444

    申请日：2008-01-02

    申请人： Giuseppe La Rosa ,  Kevin Kolvenbach ,  Ping-Chuan Wang ,  Stephen D. Wyatt

    发明人： Giuseppe La Rosa ,  Kevin Kolvenbach ,  Ping-Chuan Wang ,  Stephen D. Wyatt

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2858 ,  G01R31/2856

    摘要： A method and apparatus for dynamic characterization of reliability wearout mechanisms is disclosed. The system comprises an integrated circuit incorporating a device under test to be measured, structure for inputting a waveform to the device under test for a first predetermined time interval, structure for disabling the inputting of the waveform to the device under test, structure for measuring one or more fundamental parameters of the device under test after a second predetermined time interval, and structure for calculating an aging estimate of the device under test without the influence of recovery effect based on the one or more measured fundamental parameters. The time between stressing and measurement is precisely controlled, providing for repeatable experiments, and serves to minimize measurement error caused by recovery effects.

    摘要翻译： 公开了用于动态表征可靠性损耗机制的方法和装置。 该系统包括结合被测器件的集成电路，用于以第一预定时间间隔向待测器件输入波形的结构，用于禁止将波形输入到被测器件的结构，用于测量一个 或更多的基本参数，以及在不受基于一个或多个测量的基本参数的恢复效果的影响下计算被测设备的老化估计的结构。 压力和测量之间的时间被精确控制，提供可重复的实验，并且用于最小化由恢复效果引起的测量误差。

    Line monitoring of negative bias temperature instabilities by hole injection methods
    9.
    发明授权
    Line monitoring of negative bias temperature instabilities by hole injection methods 失效
    通过空穴注入法线性监测负偏压温度不稳定性

    公开(公告)号：US06521469B1

    公开(公告)日：2003-02-18

    申请号：US09668987

    申请日：2000-09-25

    申请人： Giuseppe La Rosa ,  Fernando J. Guarin ,  Stewart E. Rauch, III

    发明人： Giuseppe La Rosa ,  Fernando J. Guarin ,  Stewart E. Rauch, III

    IPC分类号： H01L2166

    CPC分类号： H01L22/14

    摘要： A process for in-line testing of a metal-oxide-semiconductor field effect transistor (MOSFET) device for negative bias thermal instability (NBTI), which degrades the gate oxide of the MOSFET device. The process generally comprises four steps. First, a hole injection method is selected that produces approximately the same gate oxide degradation as the NBTI under test. Second, a correlation is established between the NBTI degradation and device shifts due to the selected hole injection degradation method. Third, an in-line procedure is developed based on the hole injection method, using the second step to relate the measured shift to NBTI. Finally, a NBTI specification is defined based on the hole injection method using the second step. The MOSFET device is preferably a p-type MOSFET device and the hole injection method is preferably a channel hot-carrier stress method.

    摘要翻译： 用于负偏压热不稳定性（NBTI）的金属氧化物半导体场效应晶体管（MOSFET）器件的在线测试的过程，其降低MOSFET器件的栅极氧化物。 该方法通常包括四个步骤。 首先，选择产生与测试中的NBTI大致相同的栅极氧化物降解的空穴注入方法。 其次，由于所选择的空穴注入降解方法，在NBTI劣化和器件移位之间建立了相关性。 第三，基于空穴注入方法开发了一种在线程序，使用第二步将测量的移位与NBTI相关联。 最后，基于使用第二步骤的空穴注入方法来定义NBTI规范。 MOSFET器件优选为p型MOSFET器件，并且空穴注入法优选为沟道热载流子应力法。