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公开(公告)号：US07805274B2
公开(公告)日：2010-09-28
申请号：US11559120
申请日：2006-11-13
IPC分类号： G01N25/20
CPC分类号： G01N25/18
摘要： A method comprises determining a poly-gate temperature for a given device and determining channel temperatures of monitor devices. The method further includes extrapolating channel temperatures of the monitor devices to obtain a channel temperature for the given device. The difference in temperature (ΔT value) is determined for the given device based on the poly-gate temperature and the channel temperature. A device comprises a heating device having a poly gate with at least one contact at each end thereof and a plurality of monitor device spaced at known distances from the heating device
摘要翻译： 一种方法包括确定给定装置的多栅极温度并确定监测装置的通道温度。 该方法还包括外推监视器装置的通道温度以获得给定装置的通道温度。 基于多栅极温度和通道温度，为给定器件确定温度差（＆Dgr; T值）。 一种装置包括加热装置，该加热装置具有在其两端具有至少一个触点的多晶硅栅极以及与加热装置隔开已知距离的多个监测装置
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公开(公告)号：US20080112458A1
公开(公告)日：2008-05-15
申请号：US11559120
申请日：2006-11-13
IPC分类号： G01N25/20
CPC分类号： G01N25/18
摘要： A method comprises determining a poly-gate temperature for a given device and determining channel temperatures of monitor devices. The method further includes extrapolating channel temperatures of the monitor devices to obtain a channel temperature for the given device. The difference in temperature (ΔT value) is determined for the given device based on the poly-gate temperature and the channel temperature. A device comprises a heating device having a poly gate with at least one contact at each end thereof and a plurality of monitor device spaced at known distances from the heating device
摘要翻译： 一种方法包括确定给定装置的多栅极温度并确定监测装置的通道温度。 该方法还包括外推监测装置的通道温度以获得给定装置的通道温度。 基于多栅极温度和通道温度，为给定器件确定温度差（DeltaT值）。 一种装置包括加热装置，该加热装置具有在其两端具有至少一个触点的多晶硅栅极以及与加热装置隔开已知距离的多个监测装置
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3.发明授权Method and apparatus for dynamic characterization of reliability wearout mechanisms 失效用于动态表征可靠性损耗机制的方法和装置公开(公告)号：US07710141B2
公开(公告)日：2010-05-04
申请号：US11968444
申请日：2008-01-02
IPC分类号： G01R31/26
CPC分类号： G01R31/2858 , G01R31/2856
摘要： A method and apparatus for dynamic characterization of reliability wearout mechanisms is disclosed. The system comprises an integrated circuit incorporating a device under test to be measured, structure for inputting a waveform to the device under test for a first predetermined time interval, structure for disabling the inputting of the waveform to the device under test, structure for measuring one or more fundamental parameters of the device under test after a second predetermined time interval, and structure for calculating an aging estimate of the device under test without the influence of recovery effect based on the one or more measured fundamental parameters. The time between stressing and measurement is precisely controlled, providing for repeatable experiments, and serves to minimize measurement error caused by recovery effects.
摘要翻译： 公开了用于动态表征可靠性损耗机制的方法和装置。 该系统包括结合被测器件的集成电路，用于以第一预定时间间隔向待测器件输入波形的结构，用于禁止将波形输入到被测器件的结构，用于测量一个 或更多的基本参数，以及在不受基于一个或多个测量的基本参数的恢复效果的影响下计算被测设备的老化估计的结构。 压力和测量之间的时间被精确控制，提供可重复的实验，并且用于最小化由恢复效果引起的测量误差。
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4.发明申请METHOD AND APPARATUS FOR DYNAMIC CHARACTERIZATION OF RELIABILITY WEAROUT MECHANISMS 失效用于动态表征可靠性磨损机制的方法和装置公开(公告)号：US20090167336A1
公开(公告)日：2009-07-02
申请号：US11968444
申请日：2008-01-02
IPC分类号： G01R31/02
CPC分类号： G01R31/2858 , G01R31/2856
摘要： A method and apparatus for dynamic characterization of reliability wearout mechanisms is disclosed. The system comprises an integrated circuit incorporating a device under test to be measured, structure for inputting a waveform to the device under test for a first predetermined time interval, structure for disabling the inputting of the waveform to the device under test, structure for measuring one or more fundamental parameters of the device under test after a second predetermined time interval, and structure for calculating an aging estimate of the device under test without the influence of recovery effect based on the one or more measured fundamental parameters. The time between stressing and measurement is precisely controlled, providing for repeatable experiments, and serves to minimize measurement error caused by recovery effects.
摘要翻译： 公开了用于动态表征可靠性损耗机制的方法和装置。 该系统包括结合被测器件的集成电路，用于以第一预定时间间隔向待测器件输入波形的结构，用于禁止向被测器件输入波形的结构，用于测量一个 或更多的基本参数，以及在不受基于一个或多个测量的基本参数的恢复效果的影响下计算被测设备的老化估计的结构。 压力和测量之间的时间被精确控制，提供可重复的实验，并且用于最小化由恢复效果引起的测量误差。
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5.发明申请STRUCTURE AND METHOD FOR THERMALLY STRESSING OR TESTING A SEMICONDUCTOR DEVICE 有权用于热应力或测试半导体器件的结构和方法公开(公告)号：US20070235769A1
公开(公告)日：2007-10-11
申请号：US11307324
申请日：2006-02-01
申请人： Giuseppe La Rosa , Kevin Kolvenbach , John Massey , Ping-Chuan Wang , Kai Xiu
发明人： Giuseppe La Rosa , Kevin Kolvenbach , John Massey , Ping-Chuan Wang , Kai Xiu
IPC分类号： H01L29/76
CPC分类号： G01R31/2856
摘要： A structure is provided which includes at least one semiconductor device and a diffusion heater in a continuous active semiconductor area of a substrate. One or more semiconductor devices are provided in a first region of the active semiconductor area and a diffusion heater is disposed adjacent thereto which consists essentially of a semiconductor material included in the active semiconductor area. Conductive isolation between the first region and the diffusion heater is achieved through use of a separating gate. The separating gate overlies an intermediate region of the active semiconductor area between the first region and the diffusion heater and the separating gate is biasable to conductively isolate the first region from the diffusion heater.
摘要翻译： 提供了一种在衬底的连续有源半导体区域中包括至少一个半导体器件和扩散加热器的结构。 一个或多个半导体器件设置在有源半导体区域的第一区域中，并且扩散加热器邻近设置，其主要由包含在有源半导体区域中的半导体材料组成。 通过使用分离栅极实现第一区域和扩散加热器之间的导电隔离。 分离栅极覆盖在第一区域和扩散加热器之间的有源半导体区域的中间区域，并且分离栅极可偏置以将第一区域与扩散加热器导电隔离。
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公开(公告)号：US20110193199A1
公开(公告)日：2011-08-11
申请号：US12702463
申请日：2010-02-09
CPC分类号： H01L25/0657 , H01L21/76898 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/10253 , H01L2924/1301 , H01L2924/1305 , H01L2924/00 , H01L2224/05552
摘要： A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.
摘要翻译： 贯穿衬底通孔（TSV）结构包括至少两个嵌入衬底中的导电通路段，并且通过它们之间的导电阻挡层彼此分离。 每个单独的导电通路段的长度通常等于或小于导电材料的漂浮长度，使得由每个导电阻挡层产生的应力引起的后向流动力抵消每个导电通路段中的电迁移力 。 因此，TSV结构免于电迁移，并且在三维堆叠的芯片之间提供可靠的电连接。
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公开(公告)号：US08304863B2
公开(公告)日：2012-11-06
申请号：US12702463
申请日：2010-02-09
IPC分类号： H01L29/40
CPC分类号： H01L25/0657 , H01L21/76898 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/10253 , H01L2924/1301 , H01L2924/1305 , H01L2924/00 , H01L2224/05552
摘要： A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.
摘要翻译： 贯穿衬底通孔（TSV）结构包括至少两个嵌入衬底中的导电通路段，并且通过它们之间的导电阻挡层彼此分离。 每个单独的导电通路段的长度通常等于或小于导电材料的漂浮长度，使得由每个导电阻挡层产生的应力引起的后向流动力抵消每个导电通路段中的电迁移力 。 因此，TSV结构免于电迁移，并且在三维堆叠的芯片之间提供可靠的电连接。
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公开(公告)号：US20120292763A1
公开(公告)日：2012-11-22
申请号：US13565416
申请日：2012-08-02
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L25/0657 , H01L21/76898 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/10253 , H01L2924/1301 , H01L2924/1305 , H01L2924/00 , H01L2224/05552
摘要： A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.
摘要翻译： 贯穿衬底通孔（TSV）结构包括至少两个嵌入衬底中的导电通路段，并且通过它们之间的导电阻挡层彼此分离。 每个单独的导电通路段的长度通常等于或小于导电材料的漂浮长度，使得由每个导电阻挡层产生的应力引起的后向流动力抵消每个导电通路段中的电迁移力 。 因此，TSV结构免于电迁移，并且在三维堆叠的芯片之间提供可靠的电连接。
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公开(公告)号：US09153558B2
公开(公告)日：2015-10-06
申请号：US13565416
申请日：2012-08-02
IPC分类号： H01L29/40 , H01L25/065 , H01L21/768 , H01L23/00
CPC分类号： H01L25/0657 , H01L21/76898 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/10253 , H01L2924/1301 , H01L2924/1305 , H01L2924/00 , H01L2224/05552
摘要： A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.
摘要翻译： 贯穿衬底通孔（TSV）结构包括至少两个嵌入衬底中的导电通路段，并且通过它们之间的导电阻挡层彼此分离。 每个单独的导电通路段的长度通常等于或小于导电材料的漂浮长度，使得由每个导电阻挡层产生的应力引起的后向流动力抵消每个导电通路段中的电迁移力 。 因此，TSV结构免于电迁移，并且在三维堆叠的芯片之间提供可靠的电连接。
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10.发明授权Ring oscillator design for MOSFET device reliability investigations and its use for in-line monitoring 失效用于MOSFET器件可靠性调查的环形振荡器设计及其在线监测中的应用公开(公告)号：US06476632B1
公开(公告)日：2002-11-05
申请号：US09599785
申请日：2000-06-22
IPC分类号： G01R3126
CPC分类号： G01R31/2824
摘要： A method of determining the effect of the degradation of MOSFET on the frequency of a Ring Oscillator (RO) consisting of an odd prime number of inverter stages, each of the inverters stages having an NMOS and a PMOS field-effect transistor is described. The method includes the steps of: a) selecting one inverter from the inverter stages of the RO, the selected inverter having testable nodes, the testable nodes being connected to inputs and outputs of the NMOS and a PMOS field-effect transistors (FET) forming the selected inverter; b) simultaneously stressing under a set of stress conditions 1) all of the NMOS FETs of each of the inverter stages, 2) all of the PMOS FETs, and 3) all of the NMOS FETs and PMOS FETs in the RO; c) measuring a shift in selected device parameters in the selected inverter; d) measuring a frequency degradation of the entire RO; and e) establishing a relationship between the shift in the device parameters and the frequency degradation and relating the relationship to a known degradation mechanism Furthermore, on-chip pass gates controlled by appropriate off-chip DC voltage signals, allow parallel DC stressing, as well as forcing an off-chip AC voltage waveform to a given MOSFET type device (either PMOSFET or NMOSFET) on every inverter stage of the RO. The RO circuit makes it possible to investigate the effect on the RO frequency degradation, caused by any DC MOSFET degradation mechanism as well as by any external AC voltage waveform known to be representative of a critical circuit operation. Thus, the dependence of the RO frequency on device degradation mechanisms activated during a critical circuit operation can be carefully investigated and quantified.
摘要翻译： 描述了确定MOSFET的劣化对由奇数素数的反相器级组成的环形振荡器（RO）的频率的影响的方法，每个反相器级具有NMOS和PMOS场效应晶体管。 该方法包括以下步骤：a）从RO的反相器级选择一个反相器，所选择的反相器具有可测试节点，可测试节点连接到NMOS的输入和输出以及形成的PMOS场效应晶体管（FET） 所选择的变频器; b）在一组应力条件下同时施加压力1）每个反相器级的所有NMOS FET，2）所有PMOS FET，以及3）RO中的所有NMOS FET和PMOS FET; c）测量所选择的变频器中所选设备参数的偏移; d）测量整个RO的频率退化; 以及e）建立器件参数的偏移与频率劣化之间的关系，并且将该关系与已知的劣化机制相关联。此外，由适当的片外直流电压信号控制的片上通过门允许并行DC应力 因为在RO的每个逆变器级上施加了片外交流电压波形到给定的MOSFET型器件（PMOSFET或NMOSFET）。 RO电路可以研究由任何DC MOSFET降解机制以及已知代表关键电路操作的任何外部AC电压波形对RO频率退化的影响。 因此，可以仔细研究和量化RO频率对在关键电路操作期间激活的器件劣化机制的依赖性。
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