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公开(公告)号:US20240275385A1
公开(公告)日:2024-08-15
申请号:US18167279
申请日:2023-02-10
发明人: Santosh SHARMA , Mei Yu Soh
IPC分类号: H03K19/0185 , H03K17/10 , H03K17/687 , H03K19/00 , H03K19/017
CPC分类号: H03K19/018535 , H03K17/102 , H03K17/6871 , H03K19/0013 , H03K19/01721
摘要: A GaN logic circuit may include an input node receiving an input voltage, a first pull up transistor pulling up an output voltage in response to the input voltage, and a first depletion mode transistor having a first gate to which a first gate voltage is applied and a second gate to which a second gate voltage is applied. The first depletion mode transistor may control the first pull up transistor in response to a gate voltage difference between the first gate voltage and the second gate voltage. The logic device may further include a capacitor having a first end coupled to the first depletion mode transistor and a second end coupled to the first pull up transistor.