公开(公告)号：US20210217850A1

公开(公告)日：2021-07-15

申请号：US16743584

申请日：2020-01-15

申请人： GLOBALFOUNDRIES U.S. INC.

发明人： Anthony K. STAMPER ,  Steven M. SHANK ,  John J. PEKARIK ,  Vibhor JAIN ,  John J. ELLIS-MONAGHAN

IPC分类号： H01L29/16 ,  H01L21/02 ,  H01L27/12 ,  H01L21/762

摘要： The present disclosure relates to semiconductor structures and, more particularly, to a wafer with crystalline silicon and trap rich polysilicon layer and methods of manufacture. The structure includes: semiconductor-on-insulator (SOI) wafer composed of a lower crystalline semiconductor layer, a polysilicon layer over the lower crystalline semiconductor layer, an upper crystalline semiconductor layer over the polysilicon layer, a buried insulator layer over the upper crystalline semiconductor layer, and a top crystalline semiconductor layer over the buried insulator layer.

公开(公告)号：US20210091214A1

公开(公告)日：2021-03-25

申请号：US16909376

申请日：2020-06-23

申请人： GLOBALFOUNDRIES U.S. INC.

发明人： Herbert HO ,  Vibhor JAIN ,  John J. PEKARIK ,  Claude ORTOLLAND ,  Judson R. HOLT ,  Qizhi LIU ,  Viorel ONTALUS

IPC分类号： H01L29/737 ,  H01L29/08 ,  H01L29/66

摘要： The present disclosure relates to semiconductor structures and, more particularly, to a device with a marker layer and methods of manufacture. The device includes: a collector region; an intrinsic base region above the collector region; an emitter region comprising emitter material and a marker layer vertically between the intrinsic base region and the emitter material; and an extrinsic base region in electrical contact with the intrinsic base region.

公开(公告)号：US20240162232A1

公开(公告)日：2024-05-16

申请号：US17985861

申请日：2022-11-13

申请人： GlobalFoundries U.S. Inc.

发明人： Vibhor JAIN ,  Crystal R. KENNEY ,  John J. PEKARIK

IPC分类号： H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L23/66

CPC分类号： H01L27/1203 ,  H01L21/76267 ,  H01L21/76283 ,  H01L21/84 ,  H01L23/66 ,  H01L2223/6672

摘要： The present disclosure relates to semiconductor structures and, more particularly, to a substrate with trap rich and low resistivity regions and methods of manufacture. The structure includes: a high resistivity semiconductor substrate; an active device over the high resistivity semiconductor substrate; and a low resistivity region floating in the high resistivity semiconductor substrate and which is below the active device.

公开(公告)号：US20220122968A1

公开(公告)日：2022-04-21

申请号：US17075056

申请日：2020-10-20

申请人： GLOBALFOUNDRIES U.S. Inc.

发明人： Vibhor JAIN ,  John J. ELLIS-MONAGHAN ,  Anthony K. STAMPER ,  Steven M. SHANK ,  John J. PEKARIK

IPC分类号： H01L27/082 ,  H01L29/06 ,  H01L29/737 ,  H01L27/06

摘要： The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.

公开(公告)号：US20210408238A1

公开(公告)日：2021-12-30

申请号：US17473164

申请日：2021-09-13

申请人： GLOBALFOUNDRIES U.S. Inc.

发明人： John J. PEKARIK ,  Vibhor JAIN

IPC分类号： H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L29/737

摘要： The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a sub-collector region; a collector region above the sub-collector region; an intrinsic base region composed of intrinsic base material located above the collector region; an emitter located above and separated from the intrinsic base material; and a raised extrinsic base having a stepped configuration and separated from and self-aligned to the emitter.

公开(公告)号：US20210104621A1

公开(公告)日：2021-04-08

申请号：US17124012

申请日：2020-12-16

申请人： GLOBALFOUNDRIES U.S. Inc.

发明人： Vibhor JAIN ,  Anthony K. STAMPER ,  Steven M. SHANK ,  John J. PEKARIK

IPC分类号： H01L29/737 ,  H01L29/06

摘要： The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having an emitter base junction with a silicon-oxygen lattice interface and methods of manufacture. The device includes: a collector region buried in a substrate; shallow trench isolation regions, which isolate the collector region buried in the substrate; a base region on the substrate and over the collector region; an emitter region composed of a single crystalline of semiconductor material and located over with the base region; and an oxide interface at a junction of the emitter region and the base region.

公开(公告)号：US20230402453A1

公开(公告)日：2023-12-14

申请号：US18231510

申请日：2023-08-08

申请人： GLOBALFOUNDRIES U.S. Inc.

发明人： Vibhor JAIN ,  John J. ELLIS-MONAGHAN ,  Anthony K. STAMPER ,  Steven M. SHANK ,  John J. PEKARIK

IPC分类号： H01L27/082 ,  H01L27/06 ,  H01L29/737 ,  H01L29/06

CPC分类号： H01L27/082 ,  H01L27/0647 ,  H01L29/737 ,  H01L29/0646

摘要： The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.

公开(公告)号：US20210217849A1

公开(公告)日：2021-07-15

申请号：US16743589

申请日：2020-01-15

申请人： GLOBALFOUNDRIES U.S. INC.

发明人： Vibhor JAIN ,  Anthony K. STAMPER ,  Steven M. SHANK ,  John J. ELLIS-MONAGHAN ,  John J. PEKARIK

IPC分类号： H01L29/10 ,  H01L27/12 ,  H01L29/78 ,  H01L21/74 ,  H01L21/84

摘要： The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors with back gate contact and buried high resistivity layer and methods of manufacture. The structure includes: a handle wafer comprising a single crystalline semiconductor region; an insulator layer over the single crystalline semiconductor region; a semiconductor layer over the insulator layer; a high resistivity layer in the handle wafer, separated from the insulator layer by the single crystalline semiconductor region; and a device on the semiconductor layer.

公开(公告)号：US20240339527A1

公开(公告)日：2024-10-10

申请号：US18296521

申请日：2023-04-06

申请人： GlobalFoundries U.S. Inc.

发明人： Judson R. HOLT ,  John J. PEKARIK ,  Anindya NATH ,  Souvick MITRA

IPC分类号： H01L29/737 ,  H01L21/322

CPC分类号： H01L29/7371 ,  H01L21/322 ,  H01L29/747 ,  H01L29/78

摘要： The present disclosure relates to semiconductor structures and, more particularly, to low capacitance, low resistance devices and methods of manufacture. The structure includes: a semiconductor substrate; a device having an active region; and a porous semiconductor material within the semiconductor substrate and surrounding the active region of the device.

公开(公告)号：US20220199525A1

公开(公告)日：2022-06-23

申请号：US17126921

申请日：2020-12-18

申请人： GLOBALFOUNDRIES U.S. Inc.

发明人： Anthony K. STAMPER ,  John J. ELLIS-MONAGHAN ,  Steven M. SHANK ,  John J. PEKARIK ,  Vibhor JAIN

IPC分类号： H01L23/525 ,  H01L27/12 ,  H01L23/532

摘要： The present disclosure relates to semiconductor structures and, more particularly, to a metal-free fuse structure and methods of manufacture. The structure includes: a first metal-free fuse structure comprising a top semiconductor material of semiconductor-on-insulator (SOI) technologies, the top semiconductor material including end portions with a first electrical resistance and a fuse portion of a second, higher electrical resistance electrically connected to the end portions; and a second metal-free fuse structure comprising the top semiconductor material of semiconductor-on-insulator (SOI) technologies, the top semiconductor material of the second metal-free fuse structure including at least a fuse portion of a lower electrical resistance than the second, higher electrical resistance.