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    Multilayered substrate obtained via wafer bonding for power applications
    1.
    发明申请
    Multilayered substrate obtained via wafer bonding for power applications 审中-公开
    通过晶片接合获得的多层基板用于电力应用

    公开(公告)号：US20060284167A1

    公开(公告)日：2006-12-21

    申请号：US11326439

    申请日：2006-01-06

    申请人： Godfrey Augustine ,  Jeffrey Hartman ,  Erica Elvey ,  Paul Tittel

    发明人： Godfrey Augustine ,  Jeffrey Hartman ,  Erica Elvey ,  Paul Tittel

    IPC分类号： H01L29/08 ,  H01L35/24 ,  H01L51/00

    CPC分类号： H01L21/2007

    摘要： A multi-layer semiconductor device utilizes the good thermal and electrical properties of a polycrystalline substrate with the electrical properties of single crystal film transferred via wafer bonding. The device structure includes a polycrystalline, e.g., silicon carbide substrate, which was polished. A planarization layer of silicon is formed on the surface, followed by chemical mechanical polishing. The substrate is then bonded to either a bulk silicon wafer or a silicon-on-insulator (SOI) wafer. The silicon (SOI) wafer is thinned to the desired thickness.

    摘要翻译： 多层半导体器件利用具有通过晶片接合转移的单晶膜的电性能的多晶衬底的良好的热和电特性。 器件结构包括被抛光的多晶，例如碳化硅衬底。 在表面上形成硅的平坦化层，然后进行化学机械抛光。 然后将衬底接合到体硅晶片或绝缘体上硅（SOI）晶片上。 将硅（SOI）晶片减薄至所需的厚度。

    Novel thinning process for 3 - dimensional integration via wafer bonding
    2.
    发明申请
    Novel thinning process for 3 - dimensional integration via wafer bonding 有权
    通过晶片接合进行三维集成的新型稀化工艺

    公开(公告)号：US20060286767A1

    公开(公告)日：2006-12-21

    申请号：US11154641

    申请日：2005-06-17

    申请人： Rowland Clarke ,  Erica Elvey ,  Silai Krishnaswamy ,  Jeffrey Hartman

    发明人： Rowland Clarke ,  Erica Elvey ,  Silai Krishnaswamy ,  Jeffrey Hartman

    IPC分类号： H01L21/30

    CPC分类号： H01L21/76256 ,  H01L21/3065 ,  Y10S438/977

    摘要： First and second semiconductor wafers are bonded together, with at least one of the wafers having a first layer of silicon, an intermediate oxide layer and a second layer of silicon. The first silicon layer is initially mechanically reduced by around 80% to 90% of its thickness. The remaining silicon layer is further reduced by a plasma etch which may leave an uneven thickness. With appropriate masking the uneven thickness is made even by a second plasma etch. Remaining silicon is removed by a dry etch with XeF2 or BrF3 to expose the intermediate oxide layer. Prior to bonding the semiconductor wafers may be provided with various semiconductor devices to which electrical connections are made through conducting vias formed through the exposed intermediate oxide layer.

    摘要翻译： 第一和第二半导体晶片被结合在一起，其中至少一个晶片具有第一层硅，中间氧化物层和第二硅层。 第一硅层最初机械地还原其厚度的大约80％至90％。 剩余的硅层通过等离子体蚀刻进一步减小，其可能留下不均匀的厚度。 通过适当的掩蔽，即使通过第二等离子体蚀刻也可以形成不均匀的厚度。 通过用XeF 2或BrF 3 3的干蚀刻除去剩余的硅，以暴露中间氧化物层。 在接合之前，半导体晶片可以设置有各种半导体器件，通过通过暴露的中间氧化物层形成的通孔来形成电连接。