公开(公告)号：US10191672B2

公开(公告)日：2019-01-29

申请号：US14885786

申请日：2015-10-16

Applicant: Google LLC

Inventor： Rama Krishna Govindaraju ,  Liqun Cheng ,  Parthasarathy Ranganathan ,  Michael R. Marty ,  Andrew Gallatin

IPC: G06F3/06 ,  G06F12/1081 ,  G06F12/0888

Abstract: An example method includes during execution of a software application by a processor, receiving, by a copy processor separate from the processor, a request for an asynchronous data copy operation to copy data within a memory accessible by the copy processor, wherein the request is received from a copy manager accessible by the software application in a user space of an operating system managing execution of the software application; in response to the request, initiating, by the copy processor, the asynchronous data copy operation; continuing execution of the software application by the processor; determining, by the copy processor, that the asynchronous data copy operation has completed; and in response to determining that the asynchronous copy operation has completed, selectively notifying, by the copy processor, the software application that the asynchronous copy operation has completed.

公开(公告)号：US10127076B1

公开(公告)日：2018-11-13

申请号：US15174319

申请日：2016-06-06

Applicant: Google LLC

Inventor： Luiz Andre Barroso ,  James Laudon ,  Michael R. Marty

IPC: G06F9/44 ,  G06F9/45 ,  G06F9/48 ,  G06F12/0875

Abstract: A method includes performing one or more operations as requested by a thread executing on a processor, the thread having a thread context; receiving a park request from the thread, the park request received following a request from the thread for a low latency resource, wherein the cache response time is less than or equal to a resource response threshold so as to allow the thread context to be stored and retrieved from the cache in less time than the portion of time it takes to complete the request for the low latency resource; storing the thread context in the cache; detecting that the resume condition has occurred; retrieving the thread context from the cache; and resuming execution of the thread.

公开(公告)号：US10481811B2

公开(公告)日：2019-11-19

申请号：US16242669

申请日：2019-01-08

Applicant: Google LLC

Inventor： Rama Krishna Govindaraju ,  Liqun Cheng ,  Parthasarathy Ranganathan ,  Michael R. Marty ,  Andrew Gallatin

IPC: G06F3/06 ,  G06F12/1081 ,  G06F12/0888

Abstract: An example method includes during execution of a software application by a processor, receiving, by a copy processor separate from the processor, a request for an asynchronous data copy operation to copy data within a memory accessible by the copy processor, wherein the request is received from a copy manager accessible by the software application in a user space of an operating system managing execution of the software application; in response to the request, initiating, by the copy processor, the asynchronous data copy operation; continuing execution of the software application by the processor; determining, by the copy processor, that the asynchronous data copy operation has completed; and in response to determining that the asynchronous copy operation has completed, selectively notifying, by the copy processor, the software application that the asynchronous copy operation has completed.

公开(公告)号：US10684970B1

公开(公告)日：2020-06-16

申请号：US15921795

申请日：2018-03-15

Applicant: Google LLC

Inventor： Benjamin C. Serebrin ,  Michael R. Marty ,  Paul Jack Turner

IPC: G06F13/24 ,  G06F9/48 ,  G06F9/38 ,  G06F9/50 ,  G06F9/32

Abstract: A method includes for each processed interrupt: identifying an interrupt associated with a first interrupt number; determining that the interrupt is designated as a special interrupt, the special interrupt being an interrupt to be translated to a different interrupt number only if the hardware processor is in user mode; determining a current execution mode for the hardware processor; for each interrupt in operating system mode, delivering the interrupt as the first interrupt number; and for each interrupt in user mode: translating the first interrupt number to a second interrupt number; and delivering the interrupt as the second interrupt number, wherein the current execution mode is determined to be an operating system mode for at least one of the interrupts, and the current execution mode is determined to be a user mode for at least an additional one of the interrupts.

公开(公告)号：US20190163381A1

公开(公告)日：2019-05-30

申请号：US16242669

申请日：2019-01-08

Applicant: Google LLC

Inventor： Rama Krishna Govindaraju ,  Liqun Cheng ,  Parthasarathy Ranganathan ,  Michael R. Marty ,  Andrew Gallatin

IPC: G06F3/06 ,  G06F12/1081

Abstract: An example method includes during execution of a software application by a processor, receiving, by a copy processor separate from the processor, a request for an asynchronous data copy operation to copy data within a memory accessible by the copy processor, wherein the request is received from a copy manager accessible by the software application in a user space of an operating system managing execution of the software application; in response to the request, initiating, by the copy processor, the asynchronous data copy operation; continuing execution of the software application by the processor; determining, by the copy processor, that the asynchronous data copy operation has completed; and in response to determining that the asynchronous copy operation has completed, selectively notifying, by the copy processor, the software application that the asynchronous copy operation has completed.

公开(公告)号：US09965413B1

公开(公告)日：2018-05-08

申请号：US15454654

申请日：2017-03-09

Applicant: Google LLC

Inventor： Benjamin C. Serebrin ,  Michael R. Marty ,  Paul Jack Turner

IPC: G06F13/24 ,  G06F9/48 ,  G06F9/32 ,  G06F9/50 ,  G06F9/38

CPC classification number: G06F13/24 ,  G06F9/327 ,  G06F9/3857 ,  G06F9/4812 ,  G06F9/5027

Abstract: A method includes for each processed interrupt: identifying an interrupt associated with a first interrupt number; determining that the interrupt is designated as a special interrupt, the special interrupt being an interrupt to be translated to a different interrupt number only if the hardware processor is in user mode; determining a current execution mode for the hardware processor; for each interrupt in operating system mode, delivering the interrupt as the first interrupt number; and for each interrupt in user mode: translating the first interrupt number to a second interrupt number; and delivering the interrupt as the second interrupt number, wherein the current execution mode is determined to be an operating system mode for at least one of the interrupts, and the current execution mode is determined to be a user mode for at least an additional one of the interrupts.