公开(公告)号：US20110233635A1

公开(公告)日：2011-09-29

申请号：US13005947

申请日：2011-01-13

申请人： Gordon M. Grivna ,  Gary H. Loechelt ,  John Michael Parsey, JR. ,  Mohammed Tanvir Quddus

发明人： Gordon M. Grivna ,  Gary H. Loechelt ,  John Michael Parsey, JR. ,  Mohammed Tanvir Quddus

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L27/06

CPC分类号： H01L29/7813 ,  H01L21/76232 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734

摘要： In one embodiment, a semiconductor device is formed having a trench structure. The trench structure includes a single crystalline semiconductor plug formed along exposed upper surfaces of the trench. In one embodiment, the single crystalline semiconductor plug seals the trench to form a sealed core.

摘要翻译： 在一个实施例中，形成具有沟槽结构的半导体器件。 沟槽结构包括沿着沟槽的暴露的上表面形成的单晶半导体插塞。 在一个实施例中，单晶半导体插塞密封沟槽以形成密封的芯。

公开(公告)号：US07902075B2

公开(公告)日：2011-03-08

申请号：US12206541

申请日：2008-09-08

申请人： Gordon M. Grivna ,  Gary H. Loechelt ,  John Michael Parsey, Jr. ,  Mohammed Tanvir Quddus

发明人： Gordon M. Grivna ,  Gary H. Loechelt ,  John Michael Parsey, Jr. ,  Mohammed Tanvir Quddus

IPC分类号： H01L21/00

CPC分类号： H01L29/7813 ,  H01L21/76232 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734

摘要： In one embodiment, a semiconductor device is formed having a trench structure. The trench structure includes a single crystalline semiconductor plug formed along exposed upper surfaces of the trench. In one embodiment, the single crystalline semiconductor plug seals the trench to form a sealed core.

摘要翻译： 在一个实施例中，形成具有沟槽结构的半导体器件。 沟槽结构包括沿着沟槽的暴露的上表面形成的单晶半导体插塞。 在一个实施例中，单晶半导体插塞密封沟槽以形成密封的芯。

公开(公告)号：US08106436B2

公开(公告)日：2012-01-31

申请号：US13005947

申请日：2011-01-13

申请人： Gordon M. Grivna ,  Gary H. Loechelt ,  John Michael Parsey, Jr. ,  Mohammed Tanvir Quddus

发明人： Gordon M. Grivna ,  Gary H. Loechelt ,  John Michael Parsey, Jr. ,  Mohammed Tanvir Quddus

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L29/7813 ,  H01L21/76232 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734

摘要： In one embodiment, a semiconductor device is formed having a trench structure. The trench structure includes a single crystalline semiconductor plug formed along exposed upper surfaces of the trench. In one embodiment, the single crystalline semiconductor plug seals the trench to form a sealed core.

摘要翻译： 在一个实施例中，形成具有沟槽结构的半导体器件。 沟槽结构包括沿着沟槽的暴露的上表面形成的单晶半导体插塞。 在一个实施例中，单晶半导体插塞密封沟槽以形成密封的芯。

公开(公告)号：US20100059815A1

公开(公告)日：2010-03-11

申请号：US12206541

申请日：2008-09-08

申请人： Gordon M. Grivna ,  Gary H. Loechelt ,  John Michael Parsey, JR. ,  Mohammed Tanvir Quddus

发明人： Gordon M. Grivna ,  Gary H. Loechelt ,  John Michael Parsey, JR. ,  Mohammed Tanvir Quddus

IPC分类号： H01L29/78 ,  H01L27/06 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/76232 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734

摘要： In one embodiment, a semiconductor device is formed having a trench structure. The trench structure includes a single crystalline semiconductor plug formed along exposed upper surfaces of the trench. In one embodiment, the single crystalline semiconductor plug seals the trench to form a sealed core.

摘要翻译： 在一个实施例中，形成具有沟槽结构的半导体器件。 沟槽结构包括沿着沟槽的暴露的上表面形成的单晶半导体插塞。 在一个实施例中，单晶半导体插塞密封沟槽以形成密封的芯。

公开(公告)号：US20130153988A1

公开(公告)日：2013-06-20

申请号：US13327454

申请日：2011-12-15

申请人： Gary H. Loechelt ,  Gordon M. Grivna

发明人： Gary H. Loechelt ,  Gordon M. Grivna

IPC分类号： H01L29/78 ,  H01L21/308

CPC分类号： H01L21/3086 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/743 ,  H01L29/401 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66659 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7816 ,  H01L29/7835

摘要： An electronic device can include a transistor structure including a semiconductor layer overlying a substrate and a trench extending into the semiconductor layer having a tapered shape. In an embodiment, the tapered shape includes a facet. The transistor structure can include a source region and a drain region wherein different portions of the drain regions are disposed adjacent to the primary surface and within the trench. In another embodiment, different facets may be spaced apart from each other. Processes of forming the tapered etch can be tailored based on the needs or desires of a fabricator.

摘要翻译： 电子器件可以包括晶体管结构，其包括覆盖衬底的半导体层和延伸到具有锥形形状的半导体层的沟槽。 在一个实施例中，锥形形状包括小面。 晶体管结构可以包括源极区域和漏极区域，其中漏极区域的不同部分邻近主要表面设置并且在沟槽内。 在另一个实施例中，不同的刻面可以彼此间隔开。 可以根据制造商的需要或期望来定制形成锥形蚀刻的工艺。

公开(公告)号：US20110193160A1

公开(公告)日：2011-08-11

申请号：US12702055

申请日：2010-02-08

申请人： Gary H. Loechelt ,  Gordon M. Grivna ,  Peter J. Zdebel

发明人： Gary H. Loechelt ,  Gordon M. Grivna ,  Peter J. Zdebel

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/66696 ,  H01L21/26586 ,  H01L21/2815 ,  H01L21/743 ,  H01L21/823475 ,  H01L27/1203 ,  H01L29/0626 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1008 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/42376 ,  H01L29/6625 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/735 ,  H01L29/7824 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electronic device can include a buried conductive region, a buried insulating layer over the buried conductive region, and a semiconductor layer disposed over the buried insulating layer, wherein the semiconductor layer has a primary surface and an opposing surface, and the buried conductive region is disposed closer to the opposing surface than to the primary surface. The electronic device can also include a current-carrying electrode of a first transistor, wherein the current carrying electrode is disposed along the primary surface and spaced apart from the buried conductive layer. The electronic device can also include a vertical conductive structure extending through the buried insulating layer, wherein the vertical conductive structure is electrically connected to the current-carrying electrode and the buried conductive region.

摘要翻译： 电子器件可以包括掩埋导电区域，掩埋导电区域上的掩埋绝缘层和设置在掩埋绝缘层上的半导体层，其中半导体层具有主表面和相对表面，并且掩埋导电区域 相对于主表面更靠近对置的表面。 电子设备还可以包括第一晶体管的载流电极，其中载流电极沿着主表面设置并与掩埋的导电层间隔开。 电子器件还可以包括延伸穿过掩埋绝缘层的垂直导电结构，其中垂直导电结构电连接到载流电极和掩埋导电区域。

公开(公告)号：US08530299B2

公开(公告)日：2013-09-10

申请号：US13353223

申请日：2012-01-18

申请人： Gary H. Loechelt ,  Gordon M. Grivna

发明人： Gary H. Loechelt ,  Gordon M. Grivna

IPC分类号： H01L21/8238

CPC分类号： H01L21/823892 ,  H01L21/2815 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/66696 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electronic device including an integrated circuit can include a buried conductive region and a semiconductor layer overlying the buried conductive region, and a vertical conductive structure extending through the semiconductor layer and electrically connected to the buried conductive region. The integrated circuit can further include a doped structure having an opposite conductivity type as compared to the buried conductive region, lying closer to an opposing surface than to a primary surface of the semiconductor layer, and being electrically connected to the buried conductive region. The integrated circuit can also include a well region that includes a portion of the semiconductor layer, wherein the portion overlies the doped structure and has a lower dopant concentration as compared to the doped structure. In other embodiment, the doped structure can be spaced apart from the buried conductive region.

摘要翻译： 包括集成电路的电子设备可以包括掩埋导电区域和覆盖掩埋导电区域的半导体层，以及延伸穿过半导体层并电连接到掩埋导电区域的垂直导电结构。 集成电路还可以包括与掩埋导电区相比具有相对导电类型的掺杂结构，其比与半导体层的主表面更接近于相对表面，并且电连接到掩埋导电区。 集成电路还可以包括包括半导体层的一部分的阱区，其中该部分覆盖掺杂结构并且与掺杂结构相比具有较低的掺杂剂浓度。 在另一个实施例中，掺杂结构可以与掩埋的导电区域间隔开。

公开(公告)号：US07902601B2

公开(公告)日：2011-03-08

申请号：US12335730

申请日：2008-12-16

申请人： Gary H. Loechelt ,  John M. Parsey, Jr. ,  Peter J. Zdebel ,  Gordon M. Grivna

发明人： Gary H. Loechelt ,  John M. Parsey, Jr. ,  Peter J. Zdebel ,  Gordon M. Grivna

IPC分类号： H01L29/66

CPC分类号： H01L21/761 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0646 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7811 ,  Y10S257/90

摘要： In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.

摘要翻译： 在一个实施例中，半导体器件形成在半导体材料体中。 半导体器件包括形成在器件的有效部分附近的电荷补偿沟槽。 电荷补偿沟槽包括填充有包括相反导电类型层的各种半导体材料层的沟槽。

公开(公告)号：US20100327350A1

公开(公告)日：2010-12-30

申请号：US12495250

申请日：2009-06-30

申请人： Gary H. Loechelt ,  Gordon M. Grivna

发明人： Gary H. Loechelt ,  Gordon M. Grivna

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/088 ,  H01L21/2815 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823892 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/10 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/41708 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/6625 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/66696 ,  H01L29/735 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electronic device, including an integrated circuit, can include a buried conductive region and a semiconductor layer overlying the buried conductive region, wherein the semiconductor layer has a primary surface and an opposing surface lying closer to the buried conductive region. The electronic device can also include a first doped region and a second doped region spaced apart from each other, wherein each is within the semiconductor layer and lies closer to primary surface than to the opposing surface. The electronic device can include current-carrying electrodes of transistors. A current-carrying electrode of a particular transistor includes the first doped region and is a source or an emitter and is electrically connected to the buried conductive region. Another current-carrying electrode of a different transistor includes the second doped region and is a drain or a collector and is electrically connected to the buried conductive region.

摘要翻译： 包括集成电路的电子器件可以包括掩埋导电区域和覆盖掩埋导电区域的半导体层，其中半导体层具有更靠近掩埋导电区域的主表面和相对表面。 电子器件还可以包括彼此间隔开的第一掺杂区域和第二掺杂区域，其中每个在半导体层内并且比相对表面更靠近主表面。 电子装置可以包括晶体管的载流电极。 特定晶体管的载流电极包括第一掺杂区域，并且是源极或发射极，并且电连接到掩埋导电区域。 不同晶体管的另一载流电极包括第二掺杂区，并且是漏极或集电极，并且电连接到掩埋导电区。

公开(公告)号：US20100327347A1

公开(公告)日：2010-12-30

申请号：US12495278

申请日：2009-06-30

申请人： Gary H. Loechelt ,  Gordon M. Grivna

发明人： Gary H. Loechelt ,  Gordon M. Grivna

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/823892 ,  H01L21/2815 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/66696 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electronic device including an integrated circuit can include a buried conductive region and a semiconductor layer overlying the buried conductive region, and a vertical conductive structure extending through the semiconductor layer and electrically connected to the buried conductive region. The integrated circuit can further include a doped structure having an opposite conductivity type as compared to the buried conductive region, lying closer to an opposing surface than to a primary surface of the semiconductor layer, and being electrically connected to the buried conductive region. The integrated circuit can also include a well region that includes a portion of the semiconductor layer, wherein the portion overlies the doped structure and has a lower dopant concentration as compared to the doped structure. In other embodiment, the doped structure can be spaced apart from the buried conductive region.

摘要翻译： 包括集成电路的电子设备可以包括掩埋导电区域和覆盖掩埋导电区域的半导体层，以及延伸穿过半导体层并电连接到掩埋导电区域的垂直导电结构。 集成电路还可以包括与掩埋导电区相比具有相对导电类型的掺杂结构，其比与半导体层的主表面更接近于相对表面，并且电连接到掩埋导电区。 集成电路还可以包括包括半导体层的一部分的阱区，其中该部分覆盖掺杂结构并且与掺杂结构相比具有较低的掺杂剂浓度。 在另一个实施例中，掺杂结构可以与掩埋的导电区域间隔开。