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    Highly selective chemical dry etching of silicon nitride over silicon and silicon dioxide
    1.
    发明授权
    Highly selective chemical dry etching of silicon nitride over silicon and silicon dioxide 失效
    氮化硅在硅和二氧化硅上的高选择性化学干蚀刻

    公开(公告)号：US06060400A

    公开(公告)日：2000-05-09

    申请号：US48848

    申请日：1998-03-26

    申请人： Gottlieb S. Oehrlein ,  Bernd Kastenmeier ,  Peter Matsuo

    发明人： Gottlieb S. Oehrlein ,  Bernd Kastenmeier ,  Peter Matsuo

    IPC分类号： H01L21/311 ,  H01L21/3065

    CPC分类号： H01L21/31116

    摘要： A dry etch process is described for removing silicon nitride masks from silicon dioxide or silicon for use in a semiconductor fabrication process. A remote plasma oxygen/nitrogen discharge is employed with small additions of a fluorine source. The gas mixture is controlled so that atomic fluorine within the reaction chamber is maintained at very low flows compared with the oxygen and nitrogen reactants. Parameters are controlled so that an oxidized reactive layer is formed above any exposed silicon within a matter of seconds from initiating etching of the silicon nitride. Etch rates of silicon nitride to silicon of greater than 30:1 are described, as well as etch rates of silicon nitride to silicon dioxide of greater than 70:1.

    摘要翻译： 描述了用于从半导体制造工艺中用于从二氧化硅或硅去除氮化硅掩模的干蚀刻工艺。 远程等离子体氧/氮排放采用少量的氟源。 控制气体混合物，使得与氧和氮反应物相比，反应室内的原子氟保持在非常低的流量。 控制参数，使得在开始蚀刻氮化硅的几秒钟内，在任何暴露的硅上形成氧化的反应层。 描述了大于30:1的氮化硅与硅的蚀刻速率以及大于70:1的氮化硅与二氧化硅的蚀刻速率。

    Air gaps between conductive lines for reduced RC delay of integrated circuits
    2.
    发明授权
    Air gaps between conductive lines for reduced RC delay of integrated circuits 有权
    导线之间的气隙用于减少集成电路的RC延迟

    公开(公告)号：US07125782B2

    公开(公告)日：2006-10-24

    申请号：US10965370

    申请日：2004-10-14

    申请人： Andreas Knorr ,  Bernd Kastenmeier ,  Naim Moumen

    发明人： Andreas Knorr ,  Bernd Kastenmeier ,  Naim Moumen

    IPC分类号： H01L21/764

    CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of forming air gaps or porous dielectric materials between interconnects of integrated circuits and structures thereof. Air gaps or highly porous dielectric material having a dielectric constant of close to or equal to 1.0 are formed in a first region but not a second region of an interconnect layer. The air gaps or highly porous dielectric material are formed by depositing a first insulating material comprising an energy-sensitive material over a workpiece, depositing a second insulating material over the first insulating material, and exposing the workpiece to energy. At least a portion of the first insulating material in the first region is removed through the second insulating material. Structurally stable insulating material is disposed between conductive lines in the second region of the workpiece, providing mechanical strength for the integrated circuit.

    摘要翻译： 在集成电路的互连和其结构之间形成气隙或多孔电介质材料的方法。 介电常数接近或等于1.0的气隙或高度多孔介电材料形成在互连层的第一区域而不是第二区域中。 通过在工件上沉积包含能量敏感材料的第一绝缘材料，在第一绝缘材料上沉积第二绝缘材料，并将工件暴露于能量来形成气隙或高度多孔介电材料。 通过第二绝缘材料去除第一区域中的第一绝缘材料的至少一部分。 结构上稳定的绝缘材料设置在工件的第二区域中的导线之间，为集成电路提供机械强度。

    Sidewall sealing of porous dielectric materials
    6.
    发明授权
    Sidewall sealing of porous dielectric materials 有权
    多孔电介质材料的侧壁密封

    公开(公告)号：US07157373B2

    公开(公告)日：2007-01-02

    申请号：US10732963

    申请日：2003-12-11

    申请人： Andreas Knorr ,  Bernd Kastenmeier

    发明人： Andreas Knorr ,  Bernd Kastenmeier

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76802 ,  H01L21/76831

    摘要： A semiconductor device and method of manufacture thereof. A porous dielectric material is deposited over a workpiece. The porous dielectric material is patterned, and a photosensitive material is spun-on over the patterned porous dielectric material. A portion of the photosensitive material is formed over, and/or soaks into sidewalls of the porous dielectric material pattern, forming a barrier region of photosensitive material. The photosensitive material is developed, leaving the sidewalls of the porous dielectric material pattern sealed by the barrier region of photosensitive material. A liner is deposited over the porous dielectric material, and a conductive material such as copper is used to fill the pattern in the porous dielectric material. Diffusion of copper into the pores of the porous dielectric material is prevented by the barrier region.

    摘要翻译： 一种半导体器件及其制造方法。 多孔绝缘材料沉积在工件上。 图案化多孔电介质材料，并且在图案化的多孔介电材料上旋转感光材料。 感光材料的一部分形成在多孔电介质材料图案的上侧和/或下方，形成感光材料的阻挡区域。 显影感光材料，留下多孔电介质材料图案的侧壁由感光材料的阻挡区域密封。 衬垫沉积在多孔电介质材料上，并且诸如铜的导电材料用于填充多孔电介质材料中的图案。 通过阻挡区域阻止铜向多孔电介质材料的孔的扩散。

    Air gaps between conductive lines for reduced RC delay of integrated circuits
    7.
    发明申请
    Air gaps between conductive lines for reduced RC delay of integrated circuits 有权

    公开(公告)号：US20060081830A1

    公开(公告)日：2006-04-20

    申请号：US10965370

    申请日：2004-10-14

    申请人： Andreas Knorr ,  Bernd Kastenmeier ,  Naim Moumen

    发明人： Andreas Knorr ,  Bernd Kastenmeier ,  Naim Moumen

    IPC分类号： H01L29/04

    CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of forming air gaps or porous dielectric materials between interconnects of integrated circuits and structures thereof. Air gaps or highly porous dielectric material having a dielectric constant of close to or equal to 1.0 are formed in a first region but not a second region of an interconnect layer. The air gaps or highly porous dielectric material are formed by depositing a first insulating material comprising an energy-sensitive material over a workpiece, depositing a second insulating material over the first insulating material, and exposing the workpiece to energy. At least a portion of the first insulating material in the first region is removed through the second insulating material. Structurally stable insulating material is disposed between conductive lines in the second region of the workpiece, providing mechanical strength for the integrated circuit.

    Sidewall sealing of porous dielectric materials
    8.
    发明申请
    Sidewall sealing of porous dielectric materials 有权
    多孔电介质材料的侧壁密封

    公开(公告)号：US20050127515A1

    公开(公告)日：2005-06-16

    申请号：US10732963

    申请日：2003-12-11

    申请人： Andreas Knorr ,  Bernd Kastenmeier

    发明人： Andreas Knorr ,  Bernd Kastenmeier

    IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L23/48

    CPC分类号： H01L21/76802 ,  H01L21/76831

    摘要： A semiconductor device and method of manufacture thereof. A porous dielectric material is deposited over a workpiece. The porous dielectric material is patterned, and a photosensitive material is spun-on over the patterned porous dielectric material. A portion of the photosensitive material is formed over, and/or soaks into sidewalls of the porous dielectric material pattern, forming a barrier region of photosensitive material. The photosensitive material is developed, leaving the sidewalls of the porous dielectric material pattern sealed by the barrier region of photosensitive material. A liner is deposited over the porous dielectric material, and a conductive material such as copper is used to fill the pattern in the porous dielectric material. Diffusion of copper into the pores of the porous dielectric material is prevented by the barrier region.

    摘要翻译： 一种半导体器件及其制造方法。 多孔绝缘材料沉积在工件上。 图案化多孔电介质材料，并且在图案化的多孔介电材料上旋转感光材料。 感光材料的一部分形成在多孔电介质材料图案的上侧和/或下方，形成感光材料的阻挡区域。 显影感光材料，留下多孔电介质材料图案的侧壁由感光材料的阻挡区域密封。 衬垫沉积在多孔电介质材料上，并且诸如铜的导电材料用于填充多孔电介质材料中的图案。 通过阻挡区域阻止铜向多孔电介质材料的孔的扩散。