公开(公告)号：US5333296A

公开(公告)日：1994-07-26

申请号：US103816

申请日：1993-08-09

申请人： Gregg Bouchard ,  Lawrence Chisvin

发明人： Gregg Bouchard ,  Lawrence Chisvin

IPC分类号： F02B75/02 ,  G06F7/57 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10 ,  G06F15/80 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F9/3824 ,  G06F12/0831 ,  G06F15/8015 ,  G06F7/483 ,  G06F9/30014 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3802 ,  G06F9/3826 ,  G06F9/3832 ,  G06F9/3838 ,  G06F9/3844 ,  G06F9/3861 ,  G06F9/3867 ,  G06F9/3869 ,  G06F9/3873 ,  F02B2075/025 ,  G06F7/49947

摘要： A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroninstruction pipelining is employed (instead of microinstruction pipelining), with queuing between units of the CPU to allow flexibility in instruction execution times. A wide bandwidth is available for memory access; fetching 64-bit data blocks on each cycle. A hierarchical cache arrangement is used, increasing the likelihood of a cache hit. A writeback cache is used (instead of writethrough) and writeback is allowed to proceed even though other accesses are suppressed due to queues being full. Separate queues are provided for the return data from memory and cache invalidates, yet the order or bus transactions is maintained by a pointer arrangement. The bus protocol used by the CPU to communicate with the system bus is of the pended type, with transactions on the bus identified by an ID field specifying the originator, and arbitration for bus grant goes one simultaneously with address/data transactions on the bus.

摘要翻译： 执行可变长度指令的流水线CPU，并使用各种数据宽度引用存储器。 采用宏指令流水线（而不是微指令流水线），在CPU的单元之间排队，以允许指令执行时间的灵活性。 宽带宽可用于存储器访问; 在每个周期获取64位数据块。 使用分层缓存布置，增加高速缓存命中的可能性。 使用回写高速缓存（而不是写通），并且即使其他访问由于队列已满而被抑制，也允许回写。 提供单独的队列用于来自存储器的返回数据，并且高速缓存无效，但是顺序或总线事务由指针排列来维护。 CPU与系统总线通信使用的总线协议是挂起类型，由总线标识的总线标识的总线上的事务，总线授权的仲裁与总线上的地址/数据事务同时进行。

公开(公告)号：US20060227811A1

公开(公告)日：2006-10-12

申请号：US11218727

申请日：2005-09-02

申请人： Muhammad Hussain ,  Imran Badr ,  Faisal Masood ,  Philip Dickinson ,  Richard Kessler ,  Daniel Katz ,  Michael Bertone ,  Robert Sanzone ,  Thomas Hummel ,  Gregg Bouchard

发明人： Muhammad Hussain ,  Imran Badr ,  Faisal Masood ,  Philip Dickinson ,  Richard Kessler ,  Daniel Katz ,  Michael Bertone ,  Robert Sanzone ,  Thomas Hummel ,  Gregg Bouchard

IPC分类号： H04J3/06

CPC分类号： H04L69/16 ,  H04L49/90 ,  H04L49/9047 ,  H04L69/163

摘要： A network transport layer accelerator accelerates processing of packets so that packets can be forwarded at wire-speed. To accelerate processing of packets, the accelerator performs pre-processing on a network transport layer header encapsulated in a packet for a connection and performs in-line network transport layer checksum insertion prior to transmitting a packet. A timer unit in the accelerator schedules processing of the received packets. The accelerator also includes a free pool allocator which manages buffers for storing the received packets and a packet order unit which synchronizes processing of received packets for a same connection.

公开(公告)号：US20060075206A1

公开(公告)日：2006-04-06

申请号：US11220899

申请日：2005-09-07

申请人： Gregg Bouchard ,  David Carlson ,  Richard Kessler ,  Muhammad Hussain

发明人： Gregg Bouchard ,  David Carlson ,  Richard Kessler ,  Muhammad Hussain

IPC分类号： G06F12/10

CPC分类号： G06F9/30003 ,  H04L1/0045

摘要： A computer-readable instruction is described for traversing deterministic finite automata (DFA) graphs to perform a pattern search in the in-coming packet data in real-time. The instruction includes one or more pre-defined fields. One of the fields includes a DFA graph identifier for identifying one of several previously-stored DFA graphs. Another one of the fields includes an input reference for identifying input data to be processed using the identified DFA graphs. Yet another one of the fields includes an output reference for storing results generated responsive to the processed input data. The instructions are forwarded to a DFA engine adapted to process the input data using the identified DFA graph and to provide results as instructed by the output reference.

摘要翻译： 描述了一种用于遍历确定性有限自动机（DFA）图的计算机可读指令，以便在即将进行的分组数据中实时地执行模式搜索。 该指令包括一个或多个预定义字段。 其中一个字段包括用于标识几个先前存储的DFA图形之一的DFA图形标识符。 另一个领域包括用于使用所识别的DFA图形来识别要处理的输入数据的输入参考。 另一个领域包括用于存储响应于经处理的输入数据生成的结果的输出参考。 这些指令被转发到适用于使用识别的DFA图处理输入数据的DFA引擎，并根据输出参考的指示提供结果。

公开(公告)号：US20050055391A1

公开(公告)日：2005-03-10

申请号：US10972150

申请日：2004-10-22

申请人： David Carlson ,  Gregg Bouchard ,  Anand Varadharajan ,  Derek Brasili

发明人： David Carlson ,  Gregg Bouchard ,  Anand Varadharajan ,  Derek Brasili

IPC分类号： G06F1/02 ,  G06F7/58

CPC分类号： G06F7/588 ,  G06F7/582 ,  H04L9/0869

摘要： A random number generator comprising an entropy generator and a mixing function. The mixing function to read a seed from the entropy generator, to modify the seed, to insert the modified seed into a mixing function, to initialize a set of input variables used in the mixing function to generate a robust random number, and to generate subsequent robust random numbers using the mixing function without re-initializing any of the set of input variables.

摘要翻译： 一种包括熵发生器和混合功能的随机数发生器。 混合功能从熵发生器读取种子，修改种子，将修改后的种子插入到混合函数中，以初始化混合函数中使用的一组输入变量，以生成鲁棒的随机数，并产生后续的 使用混合函数的鲁棒随机数，而不重新初始化任何一组输入变量。

公开(公告)号：US20070038798A1

公开(公告)日：2007-02-15

申请号：US11335189

申请日：2006-01-18

申请人： Gregg Bouchard ,  David Carlson ,  Richard Kessler

发明人： Gregg Bouchard ,  David Carlson ,  Richard Kessler

IPC分类号： G06F12/08 ,  G06F7/00

CPC分类号： G06F12/06 ,  G06F12/0653 ,  G06F2212/174

摘要： Methods and apparatus are provided for selectively replicating a data structure in a low-latency memory. The memory includes multiple individual memory banks configured to store replicated copies of the same data structure. Upon receiving a request to access the stored data structure, a low-latency memory access controller selects one of the memory banks, then accesses the stored data from the selected memory bank. Selection of a memory bank can be accomplished using a thermometer technique comparing the relative availability of the different memory banks. Exemplary data structures that benefit from the resulting efficiencies include deterministic finite automata (DFA) graphs and other data structures that are loaded (i.e., read) more often than they are stored (i.e., written).

摘要翻译： 提供了用于在低延迟存储器中选择性地复制数据结构的方法和装置。 存储器包括被配置为存储相同数据结构的复制副本的多个单独存储体。 在接收到访问所存储的数据结构的请求时，低延迟存储器访问控制器选择存储体之一，然后从所选存储体存取所存储的数据。 可以使用比较不同存储体的相对可用性的温度计技术来实现存储体的选择。 受益于所产生的效率的示例性数据结构包括确定性有限自动机（DFA）图和与它们被存储（即，写入）相比更加加载（即读）的其他数据结构。

公开(公告)号：US20060085533A1

公开(公告)日：2006-04-20

申请号：US11224728

申请日：2005-09-12

申请人： Muhammad Hussain ,  David Carlson ,  Gregg Bouchard ,  Trent Parker

发明人： Muhammad Hussain ,  David Carlson ,  Gregg Bouchard ,  Trent Parker

IPC分类号： G06F15/173

CPC分类号： G06F17/30516 ,  G06F9/4498 ,  G06F17/30958 ,  G06F17/30985

摘要： An improved content search mechanism uses a graph that includes intelligent nodes avoids the overhead of post processing and improves the overall performance of a content processing application. An intelligent node is similar to a node in a DFA graph but includes a command. The command in the intelligent node allows additional state for the node to be generated and checked. This additional state allows the content search mechanism to traverse the same node with two different interpretations. By generating state for the node, the graph of nodes does not become exponential. It also allows a user function to be called upon reaching a node, which can perform any desired user tasks, including modifying the input data or position.

摘要翻译： 改进的内容搜索机制使用包括智能节点的图避免了后处理的开销，并提高了内容处理应用的整体性能。 智能节点类似于DFA图中的节点，但包含一个命令。 智能节点中的命令允许生成和检查节点的附加状态。 这种附加状态允许内容搜索机制以两种不同的解释遍历相同的节点。 通过生成节点的状态，节点的图形不会变成指数。 它还允许在到达节点时调用用户功能，节点可以执行任何所需的用户任务，包括修改输入数据或位置。

公开(公告)号：US20060059314A1

公开(公告)日：2006-03-16

申请号：US11024002

申请日：2004-12-28

申请人： Gregg Bouchard ,  David Carlson ,  Richard Kessler ,  Muhammad Hussain

发明人： Gregg Bouchard ,  David Carlson ,  Richard Kessler ,  Muhammad Hussain

IPC分类号： G06F12/00

CPC分类号： G06F9/3824 ,  G06F9/3885 ,  G06F12/0888

摘要： A content aware application processing system is provided for allowing directed access to data stored in a non-cache memory thereby bypassing cache coherent memory. The processor includes a system interface to cache coherent memory and a low latency memory interface to a non-cache coherent memory. The system interface directs memory access for ordinary load/store instructions executed by the processor to the cache coherent memory. The low latency memory interface directs memory access for non-ordinary load/store instructions executed by the processor to the non-cache memory, thereby bypassing the cache coherent memory. The non-ordinary load/store instruction can be a coprocessor instruction. The memory can be a low-latency type memory. The processor can include a plurality of processor cores.

公开(公告)号：US20060069872A1

公开(公告)日：2006-03-30

申请号：US11221408

申请日：2005-09-07

申请人： Gregg Bouchard ,  David Carlson ,  Richard Kessler ,  Muhammad Hussain

发明人： Gregg Bouchard ,  David Carlson ,  Richard Kessler ,  Muhammad Hussain

IPC分类号： G06F12/00

CPC分类号： H04L49/90 ,  G06F15/7846 ,  H04L29/06 ,  H04L63/02 ,  H04L63/04 ,  H04L63/145 ,  H04L63/164 ,  H04L69/12

摘要： A processor for traversing deterministic finite automata (DFA) graphs with incoming packet data in real-time. The processor includes at least one processor core and a DFA module operating asynchronous to the at least one processor core for traversing at least one DFA graph stored in a non-cache memory with packet data stored in a cache-coherent memory.

公开(公告)号：US20060059316A1

公开(公告)日：2006-03-16

申请号：US11030010

申请日：2005-01-05

申请人： David Asher ,  Gregg Bouchard ,  Richard Kessler ,  Robert Sanzone

发明人： David Asher ,  Gregg Bouchard ,  Richard Kessler ,  Robert Sanzone

IPC分类号： G06F13/28

CPC分类号： G06F12/084 ,  G06F9/30014 ,  G06F9/30043 ,  G06F9/30138 ,  G06F9/3824 ,  G06F9/383 ,  G06F11/3632 ,  G06F12/0804 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0835 ,  G06F12/0875 ,  G06F12/0891 ,  G06F13/24 ,  G06F2212/6012 ,  G06F2212/6022

摘要： A network services processor includes an input/output bridge that avoids unnecessary updates to memory when cache blocks storing processed packet data are no longer required. The input/output bridge monitors requests to free buffers in memory received from cores and 10 units in the network services processor. Instead of writing the cache block back to the buffer in memory that will be freed, the input/output bridge issues don't write back commands to a cache controller to clear the dirty bit for the selected cache block, thus avoiding wasteful write-backs from cache to memory. After the dirty bit is cleared, the buffer in memory is freed, that is, made available for allocation to store data for another packet.

摘要翻译： 网络服务处理器包括输入/​​输出桥，当不再需要存储处理的分组数据的高速缓存块时，避免对存储器的不必要的更新。 输入/输出桥接器监视从内核接收的内存中释放缓冲区的请求以及网络服务处理器中的10个单元。 不要将缓存块写回到将要释放的内存中的缓冲区，输入/输出桥接问题不会将命令写回缓存控制器以清除所选高速缓存块的脏位，从而避免浪费的回写 从缓存到内存。 清除脏位后，内存中的缓冲区被释放，即可用于分配以存储另一个数据包的数据。

公开(公告)号：US20060056406A1

公开(公告)日：2006-03-16

申请号：US11005490

申请日：2004-12-06

申请人： Gregg Bouchard ,  Thomas Hummel ,  Richard Kessler ,  Muhammed Hussain ,  Yen Lee

发明人： Gregg Bouchard ,  Thomas Hummel ,  Richard Kessler ,  Muhammed Hussain ,  Yen Lee

IPC分类号： H04L12/56

CPC分类号： H04L12/56 ,  H04L47/50 ,  H04L63/164 ,  H04L63/166

摘要： A method and apparatus for ordering, synchronizing and scheduling work in a multi-core network services processor is provided. Each piece of work is identified by a tag that indicates how the work is to be synchronized and ordered. Throughput is increased by processing work having different tags in parallel on different processor cores. Packet processing can be broken up into different phases, each phase having a different tag dependent on ordering and synchronization constraints for the phase. A tag switch operation initiated by a core switches a tag dependent on the phase. A dedicated tag switch bus minimizes latency for the tag switch operation.

摘要翻译： 提供了一种用于在多核网络服务处理器中排序，同步和调度工作的方法和装置。 每个工作都由一个标签标识，该标签指示工作如何同步和排序。 通过在不同的处理器核心上并行处理具有不同标签的工作来增加吞吐量。 分组处理可以分解成不同的阶段，每个阶段具有取决于阶段的排序和同步约束的不同标签。 由核心发起的标签交换操作根据相位切换标签。 专用标签交换总线最大限度地减少了标签交换操作的延迟。