公开(公告)号：US5666509A

公开(公告)日：1997-09-09

申请号：US216998

申请日：1994-03-24

申请人： Daniel M. McCarthy ,  Joseph C. Circello ,  Richard Duerden ,  Gregory C. Edgington ,  Cliff L. Parrott ,  William B. Ledbetter, Jr.

发明人： Daniel M. McCarthy ,  Joseph C. Circello ,  Richard Duerden ,  Gregory C. Edgington ,  Cliff L. Parrott ,  William B. Ledbetter, Jr.

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F12/10

CPC分类号： G06F12/0888 ,  G06F9/3861 ,  G06F12/0804 ,  G06F12/1027

摘要： A processor (10) has a data cache unit (16) wherein the data cache unit includes a memory management unit (MMU) (32). The MMU contains memory locations within transparent translation registers (TTRs), an address translation cache (40), or a table walk controller (42) which store or generate cache mode (CM) bits which indicate whether a memory access (i.e., a write operation) is precise or imprecise. Precise operations require that a first write operation or bus write instruction be executed with no other operationsnstructions executing until the first operation/instruction completes with or without a fault. Imprecise operations are operations/instruction which may be queued, partially performed, or execution simultaneously with other instructions regardless of faults or bus write operations. By allowing the logical address to determine whether the bus write operation is precise or imprecise, a large amount of system flexibility is achieved.

摘要翻译： 处理器（10）具有数据高速缓存单元（16），其中数据高速缓存单元包括存储器管理单元（MMU）（32）。 MMU包含存储或产生高速缓存模式（CM）位的透明转换寄存器（TTR），地址转换高速缓冲存储器（40）或表格移动控制器（42）内的存储单元，其指示存储器访问（即，写入 操作）精确或不准确。 精确的操作要求执行第一个写入操作或总线写入指令，直到第一个操作/指令完成或不存在故障，才执行其他操作/指令。 不精确的操作是可以与其他指令同时排队，部分执行或执行的操作/指令，而不管故障或总线写操作。 通过允许逻辑地址来确定总线写操作是精确还是不准确，实现了大量的系统灵活性。

公开(公告)号：US5530804A

公开(公告)日：1996-06-25

申请号：US242767

申请日：1994-05-16

申请人： Gregory C. Edgington ,  Joseph C. Circello ,  Daniel M. McCarthy ,  Richard Duerden

发明人： Gregory C. Edgington ,  Joseph C. Circello ,  Daniel M. McCarthy ,  Richard Duerden

IPC分类号： G06F11/26 ,  G06F11/267 ,  G06F11/36

CPC分类号： G06F11/3648 ,  G06F11/2236 ,  G06F11/261 ,  G06F12/10

摘要： A processor (10) has two modes of operation. One mode of operation is a normal mode of operation wherein the processor (10) accesses user address space or supervisor address space to perform a predetermined function. The other mode of operation is referred to as a debug, test, or emulator mode of operation and is entered via an exception/interrupt. The debug mode is an alternate operational mode of the processor (10) which has a unique debug address space which executes instructions from the normal instruction set of the processor (10). Furthermore, the debug mode of operation does not adversely affect the state of the normal mode of operation while executing debug, test, and emulation commands at normal processor speed. The debug mode is totally non-destructive and non-obtrusive to the "suspended" normal mode of operation. While in debug mode, the existing processor pipelines, bus interface, etc. are utilized.

摘要翻译： 处理器（10）具有两种操作模式。 一种操作模式是正常操作模式，其中处理器（10）访问用户地址空间或管理员地址空间以执行预定功能。 其他操作模式被称为调试，测试或仿真器操作模式，并通过异常/中断输入。 调试模式是处理器（10）的替代操作模式，其具有独特的调试地址空间，其执行来自处理器（10）的正常指令集的指令。 此外，在以正常的处理器速度执行调试，测试和仿真命令时，调试操作模式不会对正常操作模式的状态产生不利影响。 调试模式是完全非破坏性的，不违反“暂停”正常操作模式。 在调试模式下，利用现有的处理器管线，总线接口等。

公开(公告)号：US4506340A

公开(公告)日：1985-03-19

申请号：US481684

申请日：1983-04-04

申请人： Joseph C. Circello ,  Thomas H. Howell ,  Gregory C. Edgington

发明人： Joseph C. Circello ,  Thomas H. Howell ,  Gregory C. Edgington

IPC分类号： G06F7/72

CPC分类号： G06F7/722

摘要： Method and apparatus for producing the residue of the product of a multiplier and a multiplicand where the multiplier, multiplicand and product are residues with respect to a check base m, and where m=(2.sup.b -1) and b is the number of bits in a residue. An addressable memory device has at least 2 2(b-1) memory locations with each memory location having an address of 2 (b-1) bits. The address of each memory location can be considered as having two components each of (b-1) bits. The residue stored at each addressable location of the device is the residue of the product of the two components of its address. In response to each address being applied to the memory device, the residue of the product of the two components stored at the addressed memory location is read out of the device. The lower order (b-1) bits of the multiplier is applied to the device if the most significant bit of the multiplier is a logical zero. If the most significant bit of the multiplier is a logical one, the complement of the lower order (b-1) bits is applied and forms one component of the address of a memory location of the device. Similarly, the value of the most significant bit of the multiplicand determines whether the lower order (b-1) bits of the multiplicand or their complements form the other component of the address applied to the memory device. The residue read out of the addressed location is complemented to produce the residue of the product stored at the addressed memory location if and only if one of the most significant bits of the multiplier and multiplicand is a logical one, otherwise the residue read out of the memory device is the residue of the product of the multiplier and the multiplicand.

摘要翻译： 用于产生乘法器和乘法器的乘积残差的方法和装置，其中乘法器，被乘数和乘积相对于校验位m是残差，并且其中m =（2b-1）和b是位数 一个残留物 可寻址存储器件具有至少2 2（b-1）个存储器位置，每个存储器位置具有2（b-1）位的地址。 每个存储器位置的地址可以被认为具有每个（b-1）位的两个分量。 存储在设备的每个可寻址位置的残留物是其地址的两个组件的乘积的残留物。 响应于将每个地址应用于存储器设备，存储在寻址的存储器位置的两个组件的乘积的残差从设备中读出。 如果乘法器的最高有效位为逻辑0，则乘法器的低阶（b-1）位被施加到器件。 如果乘法器的最高有效位是逻辑1，则应用较低阶（b-1）位的补码，并且形成设备的存储器位置的地址的一个分量。 类似地，被乘数的最高有效位的值确定被乘数或其补码的低阶（b-1）位是否构成应用于存储器件的地址的另一分量。 补充了从寻址位置读出的残差，以产生存储在寻址的存储器位置的产品的剩余，如果且仅当乘法器和被乘数中的最高有效位之一是逻辑1，否则从 存储器件是乘法器和被乘数乘积的残差。

公开(公告)号：US4594660A

公开(公告)日：1986-06-10

申请号：US434129

申请日：1982-10-13

申请人： Russell W. Guenthner ,  Gregory C. Edgington ,  Leonard G. Trubisky ,  Joseph C. Circello

发明人： Russell W. Guenthner ,  Gregory C. Edgington ,  Leonard G. Trubisky ,  Joseph C. Circello

IPC分类号： G06F9/38 ,  G06F17/16 ,  G06F9/28

CPC分类号： G06F9/3885 ,  G06F9/3863

摘要： A collector for the results of a pipelined central processing unit of a digital data processing system. The processor has a plurality of execution units, with each execution unit executing a different set of instructions of the instruction repertoire of the processor. The execution units execute instructions issued to them in order of issuance by the pipeline and in parallel. As instructions are issued to the execution units, the operation code identifying each instruction is also issued in program order to an instruction execution queue of the collector. The results of the execution of each instruction by an execution unit are stored in a result stack associated with each execution unit. Collector control causes the results of the execution of instructions to program visible registers to be stored in a master safe store register in program order which is determined by the order of instructions stored in the instruction execution stack on a first-in, first-out basis. The collector also issues write commands to write results of the execution of instructions into memory in program order.

摘要翻译： 用于数字数据处理系统的流水线中央处理单元的结果的收集器。 处理器具有多个执行单元，每个执行单元执行处理器的指令集的不同指令集。 执行单元按照管道发布的顺序执行发给他们的指令并行执行。 当向执行单元发出指令时，识别每条指令的操作代码也以程序顺序发布到收集器的指令执行队列。 由执行单元执行每条指令的结果存储在与每个执行单元相关联的结果堆栈中。 收集器控制导致执行指令的结果将可见寄存器编程存储在主安全存储寄存器中，程序顺序由存储在指令执行堆栈中的指令顺序以先进先出为基础确定 。 收集器还发出写入命令，以按程序顺序将指令的执行结果写入存储器。