公开(公告)号：US5493241A

公开(公告)日：1996-02-20

申请号：US340252

申请日：1994-11-16

申请人： Gregory J. Landry ,  Cathal G. Phelan

发明人： Gregory J. Landry ,  Cathal G. Phelan

IPC分类号： G11C8/10 ,  G11C8/18 ,  G11C8/00 ,  H03K19/20

CPC分类号： G11C8/10 ,  G11C8/18

摘要： A memory includes a memory array and a decoder. The memory array includes a plurality of memory locations and the decoder is coupled to receive an address for decoding the address to generate a select signal for selecting one of the plurality of memory locations in the memory array for a memory operation. The memory further includes circuitry coupled to the decoder for delaying the select signal for a first predetermined delay time to generate a delayed select signal and for selectively applying one of the select signal and the delayed select signal to the memory array. The circuitry applies the delayed select signal to the memory array during the memory operation before the select signal is to be deasserted such that address hold time of the memory operation is decreased without affecting the memory operation. The circuitry includes a delay circuit for delaying the select signal, a select circuit for selecting one of the select signal and the delayed select signal to be applied to the memory array, and a resettable delay circuit for delaying a memory operation control signal for a second predetermined delay time to select one of the select signal and the delayed select signal.

摘要翻译： 存储器包括存储器阵列和解码器。 存储器阵列包括多个存储器位置，并且解码器被耦合以接收用于解码地址的地址，以产生选择信号，用于选择用于存储器操作的存储器阵列中的多个存储器位置中的一个。 存储器还包括耦合到解码器的电路，用于延迟第一预定延迟时间的选择信号以产生延迟的选择信号，并且用于选择性地将选择信号和延迟的选择信号之一施加到存储器阵列。 该电路在存储器操作期间将延迟的选择信号施加到存储器阵列，在选择信号将被取消置位之前，使存储器操作的地址保持时间减小而不影响存储器操作。 该电路包括用于延迟选择信号的延迟电路，用于选择选择信号和要施加到存储器阵列的延迟选择信号之一的选择电路，以及用于将存储器操作控制信号延迟第二个的可复位延迟电路 预定延迟时间以选择选择信号和延迟选择信号之一。

公开(公告)号：US5391941A

公开(公告)日：1995-02-21

申请号：US126069

申请日：1993-09-23

申请人： Gregory J. Landry

发明人： Gregory J. Landry

IPC分类号： H03K19/0948 ,  H03K19/20

CPC分类号： H03K19/0948

摘要： A logic circuit implementing a logic NAND function with respect to a first input signal and a second input signal is described. First and second P-channel transistors are coupled in parallel to a power supply and an output node. Each of the first and second P-channel transistors receives the respective one of the first and second input signals. A first circuit branch has a first and a second N-channel transistor. The first N-channel transistor has a first end coupled to the output node and a second end coupled to a first end of the second N-channel transistor. The second N-channel transistor has a second end coupled to ground. The first N-channel transistor receives the first input signal and the second N-channel transistor receives the second input signal. A second circuit branch has a third and a fourth N-channel transistor. The third N-channel transistor has a first end coupled to the output node and a second end coupled to a first end of the fourth N-channel transistor. The fourth N-channel transistor has a second end coupled to ground. The third N-channel transistor receives the second input signal and the fourth N-channel transistor receives the first input signal such that the logic circuit has a balanced propagation delay with respect to the first and second input signals. The logic circuit can be used to form a decoder circuit that has a balanced propagation delay for the input signals and a minimized input capacitance. The above described logic circuit can also be changed accordingly to implement a logic NOR function.

摘要翻译： 描述了相对于第一输入信号和第二输入信号实现逻辑NAND功能的逻辑电路。 第一和第二P沟道晶体管并联耦合到电源和输出节点。 第一和第二P沟道晶体管中的每一个接收第一和第二输入信号中的相应的一个。 第一电路支路具有第一和第二N沟道晶体管。 第一N沟道晶体管具有耦合到输出节点的第一端和耦合到第二N沟道晶体管的第一端的第二端。 第二N沟道晶体管具有耦合到地的第二端。 第一N沟道晶体管接收第一输入信号，第二N沟道晶体管接收第二输入信号。 第二电路支路具有第三和第四N沟道晶体管。 第三N沟道晶体管具有耦合到输出节点的第一端和耦合到第四N沟道晶体管的第一端的第二端。 第四N沟道晶体管具有耦合到地的第二端。 第三N沟道晶体管接收第二输入信号，第四N沟道晶体管接收第一输入信号，使得逻辑电路相对于第一和第二输入信号具有平衡的传播延迟。 逻辑电路可用于形成对输入信号具有平衡的传播延迟和最小的输入电容的解码器电路。 上述逻辑电路也可以相应地改变以实现逻辑NOR功能。

公开(公告)号：US06119249A

公开(公告)日：2000-09-12

申请号：US49952

申请日：1998-03-27

申请人： Gregory J. Landry

发明人： Gregory J. Landry

IPC分类号： G11C29/26 ,  G11C29/38 ,  G11C29/00

CPC分类号： G11C29/38 ,  G11C29/26

摘要： A method of testing, in parallel, a memory device including a plurality of memory cells organized into memory blocks, the memory device having a plurality of wired-OR pre-charged differential data line pairs, includes the steps of enabling a predetermined number of memory blocks at a time; writing to and reading as many bits as the predetermined number of enabled memory blocks in parallel; and detecting when both data lines of each of the wired-OR differential pairs are active at a same time, indicating that at least one bad memory cell exists within at least one of the predetermined number of enabled memory blocks. According to another embodiment, a memory device operable in both a normal and a test mode includes a plurality of memory cells organized into a plurality of blocks; at least one wired-OR pre-charged differential data line pair connected to each of the blocks; a block address decoder, the block address decoder enabling one of the plurality of blocks at a time during normal operation and more than one block at a time when the memory device is operating in test mode; and an output buffer for each of the at least one wired-OR differential pairs, the output buffer including a bad cell detector, the bad cell detector causing an output of the buffer to tri-state when a status of a differential pair connected to the buffer is indicative of at least one bad memory cell within at least one of the plurality of enabled blocks.

摘要翻译： 一种并行地测试包括组织在存储块中的多个存储器单元的存储器件的方法，所述存储器件具有多个有线或预充电的差分数据线对，包括以下步骤：使预定数量的存储器 一次阻止; 并行读取和读取与预定数量的使能存储块一样多的位; 以及检测每个所述有线或差分对的两条数据线何时同时处于活动状态，指示在所述预定数量的使能存储块中的至少一个中存在至少一个坏存储器单元。 根据另一实施例，可在正常和测试模式下操作的存储器件包括组织成多个块的多个存储器单元; 连接到每个块的至少一个有线OR预充电差分数据线对; 块地址解码器，所述块地址解码器在正常操作期间一次启用所述多个块中的一个块，并且在所述存储器件在测试模式下操作时，多于一个块; 以及用于所述至少一个有线或差分对中的每一个的输出缓冲器，所述输出缓冲器包括坏信号检测器，所述坏信元检测器使得当连接到所述差分对的差分对的状态时所述缓冲器的输出为三态 缓冲器指示所述多个使能块中的至少一个中的至少一个坏存储器单元。

公开(公告)号：US08410795B1

公开(公告)日：2013-04-02

申请号：US13549379

申请日：2012-07-13

申请人： Tao Peng ,  Gregory J. Landry ,  Xiaoping Weng ,  Yingzhu Deng

发明人： Tao Peng ,  Gregory J. Landry ,  Xiaoping Weng ,  Yingzhu Deng

IPC分类号： G01R27/26

CPC分类号： G06F3/044 ,  G06F2203/04103

摘要： A capacitive sensor array may include a first sensor element of a first plurality of sensor elements, and a second sensor element. The second sensor element may include a plurality of subelements, where each of the plurality of subelements is connected to at least another of the plurality of subelements by one of a plurality of connecting traces. A width of each of the connecting traces may be less than a width of any of the plurality of subelements. Connecting traces in a subset of the plurality of connecting traces may be staggered about a central axis of the second sensor element.

摘要翻译： 电容传感器阵列可以包括第一多个传感器元件的第一传感器元件和第二传感器元件。 第二传感器元件可以包括多个子元件，其中多个子元件中的每一个子元件通过多个连接迹线之一连接到多个子元件中的至少另一个子元件。 每个连接迹线的宽度可以小于多个子元件中的任一个的宽度。 多个连接迹线的子集中的连接迹线可以围绕第二传感器元件的中心轴交错。

公开(公告)号：US06615923B1

公开(公告)日：2003-09-09

申请号：US10198470

申请日：2002-07-17

申请人： Milford Lay, Jr. ,  Gregory J. Landry

发明人： Milford Lay, Jr. ,  Gregory J. Landry

IPC分类号： E21B2912

CPC分类号： E21B33/037

摘要： A protector for placement over subsea wellheads. A main body is cylindrical, with an inner diameter of sufficiant size to fit over a subsea wellhead. One end of the main body has a cap across it. A vent and a pump-through port, which permits pumping in of corrosion inhibitors, is in the cap. The open end of the main body has an outwardly flaring skirt to help guide the protector into place over the wellhead. The main body is formed from polyurethane via molding or other suitable methods.

摘要翻译： 一个保护者放置在海底井口。 主体是圆柱形的，内径足够大，适合海底井口。 主体的一端有一个盖子。 一个排气口和一个泵通孔，允许泵送腐蚀抑制剂，在盖子里。 主体的开口端具有向外扩张的裙部，以帮助将保护器引导到井口上的适当位置。 主体由聚氨酯通过模制或其他合适的方法形成。

公开(公告)号：US06222393B1

公开(公告)日：2001-04-24

申请号：US09357474

申请日：1999-07-20

申请人： Shailesh Shah ,  Gregory J. Landry

发明人： Shailesh Shah ,  Gregory J. Landry

IPC分类号： H03K500

CPC分类号： H03K5/1534 ,  H03K2005/00293

摘要： A circuit for generating a pulse signal in response to an input signal. The circuit provides a pulse width for the pulse signal. A first logic device receives the input signal and generates a first intermediate signal. A delay device is coupled to the first logic device and receives the first intermediate signal. The delay device generates a second intermediate signal in response to the first intermediate signal after a period of time. The second intermediate signal has the same state as the second intermediate signal. A second logic device is coupled to both the first logic device and the delay device. The second logic device generates the pulse signal in response to the first intermediate signal.

摘要翻译： 一种用于响应于输入信号产生脉冲信号的电路。 该电路为脉冲信号提供脉冲宽度。 第一逻辑装置接收输入信号并产生第一中间信号。 延迟装置耦合到第一逻辑装置并且接收第一中间信号。 延迟装置在一段时间后响应于第一中间信号产生第二中间信号。 第二中间信号具有与第二中间信号相同的状态。 第二逻辑器件耦合到第一逻辑器件和延迟器件。 第二逻辑装置响应于第一中间信号产生脉冲信号。

公开(公告)号：US5933032A

公开(公告)日：1999-08-03

申请号：US897375

申请日：1997-07-21

申请人： Shailesh Shah ,  Gregory J. Landry

发明人： Shailesh Shah ,  Gregory J. Landry

IPC分类号： H03K5/06 ,  H03K5/153 ,  H03K5/00

CPC分类号： H03K5/153 ,  H03K5/06

摘要： A circuit for generating a pulse signal in response to an input signal. The circuit provides a pulse width for the pulse signal. A first logic device receives the input signal and generates a first intermediate signal. A delay device is coupled to the first logic device and receives the first intermediate signal. The delay device generates a second intermediate signal in response to the first intermediate signal after a period of time. The second intermediate signal has the same state as the second intermediate signal. A second logic device is coupled to both the first logic device and the delay device. The second logic device generates the pulse signal in response to the first intermediate signal.

摘要翻译： 一种用于响应于输入信号产生脉冲信号的电路。 电路为脉冲信号提供脉冲宽度。 第一逻辑装置接收输入信号并产生第一中间信号。 延迟装置耦合到第一逻辑装置并且接收第一中间信号。 延迟装置在一段时间后响应于第一中间信号产生第二中间信号。 第二中间信号具有与第二中间信号相同的状态。 第二逻辑器件耦合到第一逻辑器件和延迟器件。 第二逻辑装置响应于第一中间信号产生脉冲信号。

公开(公告)号：US08436627B1

公开(公告)日：2013-05-07

申请号：US13548125

申请日：2012-07-12

申请人： Tao Peng ,  Gregory J. Landry ,  Xiaoping Weng ,  Yingzhu Deng

发明人： Tao Peng ,  Gregory J. Landry ,  Xiaoping Weng ,  Yingzhu Deng

IPC分类号： G01R27/26

CPC分类号： G06F3/044 ,  G06F2203/04103

摘要： A capacitive sensor array may include a first sensor element of a first plurality of sensor elements, and a second sensor element. The second sensor element may include a plurality of subelements, where each of the plurality of subelements is connected to at least another of the plurality of subelements by one of a plurality of connecting traces. A width of each of the connecting traces may be less than a width of any of the plurality of subelements. Connecting traces in a subset of the plurality of connecting traces may be staggered about a central axis of the second sensor element.

公开(公告)号：US06028448A

公开(公告)日：2000-02-22

申请号：US49887

申请日：1998-03-27

申请人： Gregory J. Landry

发明人： Gregory J. Landry

IPC分类号： H03K19/0185 ,  H03K19/094 ,  H03K19/00 ,  H03K19/02

CPC分类号： H03K19/01855 ,  H03K19/09429

摘要： An output buffer includes a differential data circuit for generating a first and a second differential signal, a pulse circuit for generating a pulse signal, a first latch circuit set by the first differential signal and reset by either the pulse signal or the second differential signal and a second latch circuit set by the second differential signal and reset by either the pulse signal or the first differential signal. An output circuit generates an output signal, the output signal being tri-stated whenever the pulse signal resets the first and second latch circuits. A method for improving output tri-state time of an output buffer includes the steps of pre-charging first and the second differential data inputs; tri-stating the buffer output upon each assertion of a timing signal; switching the output out of tri-state and into either a first or a second logic state only when one of the first and second differential data inputs changes to an active state; and returning to the pre-charging step. As the output of the buffer is tri-stated upon each assertion of the timing signal irrespective of whether a current cycle is a read, write cycle or de-select cycle, the switching time from one device connected to a bus to another device connected to the same bus is decreased.

摘要翻译： 输出缓冲器包括用于产生第一和第二差分信号的差分数据电路，用于产生脉冲信号的脉冲电路，由第一差分信号设置的第一锁存电路，并通过脉冲信号或第二差分信号进行复位;以及 由第二差分信号设置的第二锁存电路，并通过脉冲信号或第一差分信号进行复位。 输出电路产生输出信号，每当脉冲信号复位第一和第二锁存电路时，输出信号是三态的。 一种用于改善输出缓冲器的输出三态时间的方法，包括对第一和第二差分数据输入进行预充电的步骤; 在每次断言定时信号时，表示缓冲器输出; 只有当第一和第二差分数据输入之一变为活动状态时，将输出切换成三态并进入第一或第二逻辑状态; 并返回到预充电步骤。 由于每次断言定时信号时缓冲器的输出是三态的，无论当前周期是读周期还是读周期还是取消选择周期，从连接到总线的设备到连接到总线的另一个设备的切换时间 同一辆巴士减少。

公开(公告)号：US5490115A

公开(公告)日：1996-02-06

申请号：US282314

申请日：1994-07-29

申请人： Shailesh Shah ,  Gregory J. Landry

发明人： Shailesh Shah ,  Gregory J. Landry

IPC分类号： G11C29/34 ,  G11C7/00

CPC分类号： G11C29/34

摘要： A computer memory system incorporates a gang write circuit block to reduce the number of clock cycles required write a background pattern to memory cells during a memory test operation. The computer memory system includes (1) a two-dimensional array having multiple memory cells arranged in M rows and N columns and (2) the gang write circuit block for writing to N memory cells located in a row during one cycle and for writing to all of the memory cells in M cycles. The gang write circuit block may include two inverters for each column of the memory array and two test signals for the inverters. The background pattern may be all 1's, all 0's or some combination of 1's and 0's. The gang write circuit block becomes inactive during a normal read and write operation. When all the word lines of the computer memory system are selected, all the memory cells are written simultaneously.

摘要翻译： 计算机存储器系统包括组写入电路块，以减少在存储器测试操作期间将需要的背景图案写入存储器单元的时钟周期数。 计算机存储器系统包括（1）具有以M行和N列排列的多个存储单元的二维阵列，以及（2）用于在一个周期内向位于行中的N个存储单元写入的写入电路块， 所有存储单元都以M个循环。 该组写电路块可以包括用于存储器阵列的每一列的两个反相器和用于逆变器的两个测试信号。 背景图案可能全部为1，全部为0或1和0的某种组合。 在正常读写操作期间，该组写入电路块变为无效。 当选择计算机存储器系统的所有字线时，所有存储单元都被同时写入。