公开(公告)号：US08048812B2

公开(公告)日：2011-11-01

申请号：US12769071

申请日：2010-04-28

申请人： Luan Tran ,  William T. Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer K. Abatchev ,  Gurtej S. Sandhu ,  D. Mark Durcan

发明人： Luan Tran ,  William T. Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer K. Abatchev ,  Gurtej S. Sandhu ,  D. Mark Durcan

IPC分类号： H01L21/302

CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088

摘要： Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern. Pitch multiplication is accomplished by patterning an amorphous carbon layer. Sidewall spacers are then formed on the amorphous carbon sidewalls which are then removed; the sidewall spacers defining the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is transferred to the BARC. The combined pattern is transferred to an underlying amorphous silicon layer. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, is then etched into the underlying substrate.

摘要翻译： 通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。 间距乘法用于形成第一模式的较小特征。 通过图案化无定形碳层来实现间距倍增。 然后在非晶碳侧壁上形成侧壁间隔物，然后将其去除; 侧壁间隔物限定第一掩模图案。 然后沉积底部抗反射涂层（BARC）以形成平坦表面，并且在BARC上形成光致抗蚀剂层。 接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，其转移到BARC。 将组合图案转移到下面的非晶硅层。 然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。 然后将组合的掩模图案蚀刻到下面的基底中。

公开(公告)号：US20120256309A1

公开(公告)日：2012-10-11

申请号：US13530679

申请日：2012-06-22

申请人： Luan Tran ,  William T. Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi (Jenny) Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer K. Abatchev ,  Gurtej S. Sandhu ,  D. Mark Durcan

发明人： Luan Tran ,  William T. Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi (Jenny) Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer K. Abatchev ,  Gurtej S. Sandhu ,  D. Mark Durcan

IPC分类号： H01L23/48

CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088

摘要： An integrated circuit having differently-sized features wherein the smaller features have a pitch multiplied relationship with the larger features, which are of such size as to be formed by conventional lithography.

摘要翻译： 具有不同尺寸特征的集成电路，其中较小特征与具有通过常规光刻形成的尺寸的较大特征具有间距倍增关系。

公开(公告)号：US07771917B2

公开(公告)日：2010-08-10

申请号：US11155167

申请日：2005-06-17

申请人： Gurtej S. Sandhu ,  William T. Rericha

发明人： Gurtej S. Sandhu ,  William T. Rericha

IPC分类号： G03F7/00

CPC分类号： B29C59/16 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  G03F7/0017

摘要： A method of forming a template for use in imprint lithography. The method comprises providing an ultraviolet (“UV”) wavelength radiation transparent layer and forming a pattern in the UV transparent layer by photolithography. The pattern may be formed by anisotropically etching the UV transparent layer and may have feature dimensions of less than approximately 100 nm, such as dimensions of less than approximately 45 nm. An additional embodiment of the method comprises providing a UV opaque layer comprising a first pattern therein, forming a first UV transparent layer in contact with the first contact-pattern of the UV opaque layer, forming a second UV transparent layer in contact with the first UV transparent layer, and removing the UV opaque layer to form the template. An intermediate template structure for use in imprint lithography is also disclosed. In other embodiments, a template that is opaque to UV wavelength radiation and a method of forming the same are disclosed.

摘要翻译： 形成用于压印光刻的模板的方法。 该方法包括提供紫外（“UV”）波长辐射透明层并通过光刻在UV透明层中形成图案。 图案可以通过各向异性蚀刻UV透明层而形成，并且可以具有小于约100nm的特征尺寸，例如小于约45nm的尺寸。 该方法的另外的实施例包括提供其中包含第一图案的UV不透明层，形成与UV不透明层的第一接触图案接触的第一UV透明层，形成与第一UV接触的第二UV透明层 透明层，并除去UV不透明层以形成模板。 还公开了用于压印光刻的中间模板结构。 在其它实施例中，公开了对UV波长辐射不透明的模板及其形成方法。

公开(公告)号：US07651951B2

公开(公告)日：2010-01-26

申请号：US11681027

申请日：2007-03-01

申请人： Luan Tran ,  William T. Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer K. Abatchev ,  Gurtej S. Sandhu ,  D. Mark Durcan

发明人： Luan Tran ,  William T. Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer K. Abatchev ,  Gurtej S. Sandhu ,  D. Mark Durcan

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088

摘要： Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.

公开(公告)号：US08598632B2

公开(公告)日：2013-12-03

申请号：US13530679

申请日：2012-06-22

申请人： Luan Tran ,  William T. Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer K. Abatchev ,  Gurtej S. Sandhu ,  D. Mark Durcan

发明人： Luan Tran ,  William T. Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer K. Abatchev ,  Gurtej S. Sandhu ,  D. Mark Durcan

IPC分类号： H01L27/118

CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088

摘要： An integrated circuit having differently-sized features wherein the smaller features have a pitch multiplied relationship with the larger features, which are of such size as to be formed by conventional lithography.

摘要翻译： 具有不同尺寸特征的集成电路，其中较小特征与具有通过常规光刻形成的尺寸的较大特征具有间距倍增关系。

公开(公告)号：US20100285167A1

公开(公告)日：2010-11-11

申请号：US12839755

申请日：2010-07-20

申请人： Gurtej S. Sandhu ,  William T. Rericha

发明人： Gurtej S. Sandhu ,  William T. Rericha

IPC分类号： B29C59/16

CPC分类号： B29C59/16 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  G03F7/0017

摘要： A method of forming a template for use in imprint lithography. The method comprises providing an ultraviolet (“UV”) wavelength radiation transparent layer and forming a pattern in the UV transparent layer by photolithography. The pattern may be formed by anisotropically etching the UV transparent layer and may have feature dimensions of less than approximately 100 nm, such as dimensions of less than approximately 45 nm. An additional embodiment of the method comprises providing a UV opaque layer comprising a first pattern therein, forming a first UV transparent layer in contact with the first contact pattern of the UV opaque layer, forming a second UV transparent layer in contact with the first UV transparent layer, and removing the UV opaque layer to form the template. An intermediate template structure for use in imprint lithography is also disclosed. In other embodiments, a template that is opaque to UV wavelength radiation and a method of forming the same are disclosed.

摘要翻译： 形成用于压印光刻的模板的方法。 该方法包括提供紫外（“UV”）波长辐射透明层并通过光刻在UV透明层中形成图案。 图案可以通过各向异性蚀刻UV透明层而形成，并且可以具有小于约100nm的特征尺寸，例如小于约45nm的尺寸。 该方法的另外的实施例包括提供包括其中的第一图案的UV不透明层，形成与UV不透明层的第一接触图案接触的第一UV透明层，形成与第一UV透明接触的第二UV透明层 层，并且去除UV不透明层以形成模板。 还公开了用于压印光刻的中间模板结构。 在其它实施例中，公开了对UV波长辐射不透明的模板及其形成方法。

公开(公告)号：US20100092890A1

公开(公告)日：2010-04-15

申请号：US12636317

申请日：2009-12-11

申请人： Gurtej S. Sandhu ,  Randal W. Chance ,  William T. Rericha

发明人： Gurtej S. Sandhu ,  Randal W. Chance ,  William T. Rericha

IPC分类号： G03F7/20

CPC分类号： H01L23/50 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/1052 ,  H01L27/10894 ,  H01L2924/0002 ,  Y10S438/95 ,  Y10S438/975 ,  H01L2924/00

摘要： Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming interconnects in the periphery of the integrated circuit, are increased. The narrow mask lines are formed by pitch multiplication and the wider mask lines are formed by photolithography. The wider mask lines and are aligned so that one side of those lines is flush with or inset from a corresponding side of the narrow lines. Being wider, the opposite sides of the wider mask lines protrude beyond the corresponding opposite sides of the narrow mask lines. The wider mask lines are formed in negative photoresist having a height less than the height of the narrow mask lines. Advantageously, the narrow mask lines can prevent expansion of the mask lines in one direction, thus increasing alignment tolerances in that direction. In the other direction, use of photolithography and a shadowing effect caused by the relative heights of the photoresist and the narrow mask lines causes the wider mask lines to be formed with a rounded corner, thus increasing alignment tolerances in that direction by increasing the distance to a neighboring narrow mask line.

摘要翻译： 在集成电路的阵列区域中用于形成互连的窄掩模线之间的对准公差和用于在集成电路的外围形成互连的较宽的掩模线增加。 通过间距倍增形成窄屏蔽线，通过光刻法形成较宽的掩模线。 较宽的掩模线对准，使得这些线的一侧与窄线的相应侧齐平或嵌入。 较宽的掩模线的相对侧突出超过窄掩模线的对应的相对侧。 较宽的掩模线形成在具有小于窄掩模线的高度的高度的负光致抗蚀剂中。 有利地，窄掩模线可以防止掩模线在一个方向上的膨胀，从而增加该方向上的对准公差。 在另一个方向上，使用光刻法和由光致抗蚀剂和窄掩模线的相对高度引起的阴影效应导致较宽的掩模线形成有圆角，从而通过增加到该方向的距离来增加该方向上的对准公差 相邻的窄屏线。

公开(公告)号：US07655387B2

公开(公告)日：2010-02-02

申请号：US10934317

申请日：2004-09-02

申请人： Gurtej S. Sandhu ,  Randal W. Chance ,  William T. Rericha

发明人： Gurtej S. Sandhu ,  Randal W. Chance ,  William T. Rericha

IPC分类号： G03F7/00

CPC分类号： H01L23/50 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/1052 ,  H01L27/10894 ,  H01L2924/0002 ,  Y10S438/95 ,  Y10S438/975 ,  H01L2924/00

摘要： Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming interconnects in the periphery of the integrated circuit, are increased. The narrow mask lines are formed by pitch multiplication and the wider mask lines are formed by photolithography. The wider mask lines and are aligned so that one side of those lines is flush with or inset from a corresponding side of the narrow lines. Being wider, the opposite sides of the wider mask lines protrude beyond the corresponding opposite sides of the narrow mask lines. The wider mask lines are formed in negative photoresist having a height less than the height of the narrow mask lines. Advantageously, the narrow mask lines can prevent expansion of the mask lines in one direction, thus increasing alignment tolerances in that direction. In the other direction, use of photolithography and a shadowing effect caused by the relative heights of the photoresist and the narrow mask lines causes the wider mask lines to be formed with a rounded corner, thus increasing alignment tolerances in that direction by increasing the distance to a neighboring narrow mask line.

摘要翻译： 在集成电路的阵列区域中用于形成互连的窄掩模线之间的对准公差和用于在集成电路的外围形成互连的较宽的掩模线增加。 通过间距倍增形成窄屏蔽线，通过光刻法形成较宽的掩模线。 较宽的掩模线对准，使得这些线的一侧与窄线的相应侧齐平或嵌入。 较宽的掩模线的相对侧突出超过窄掩模线的对应的相对侧。 较宽的掩模线形成在具有小于窄掩模线的高度的高度的负光致抗蚀剂中。 有利地，窄掩模线可以防止掩模线在一个方向上的膨胀，从而增加该方向上的对准公差。 在另一个方向上，使用光刻法和由光致抗蚀剂和窄掩模线的相对高度引起的阴影效应导致较宽的掩模线形成有圆角，从而通过增加到该方向的距离来增加该方向上的对准公差 相邻的窄屏线。

公开(公告)号：US08657597B2

公开(公告)日：2014-02-25

申请号：US12839755

申请日：2010-07-20

申请人： Gurtej S. Sandhu ,  William T. Rericha

发明人： Gurtej S. Sandhu ,  William T. Rericha

IPC分类号： A01J21/00

CPC分类号： B29C59/16 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  G03F7/0017

摘要： A method of forming a template for use in imprint lithography. The method comprises providing an ultraviolet (“UV”) wavelength radiation transparent layer and forming a pattern in the UV transparent layer by photolithography. The pattern may be formed by anisotropically etching the UV transparent layer and may have feature dimensions of less than approximately 100 nm, such as dimensions of less than approximately 45 nm. An additional embodiment of the method comprises providing a UV opaque layer comprising a first pattern therein, forming a first UV transparent layer in contact with the first pattern of the UV opaque layer, forming a second UV transparent layer in contact with the first UV transparent layer, and removing the UV opaque layer to form the template. An intermediate template structure for use in imprint lithography is also disclosed. In other embodiments, a template that is opaque to UV wavelength radiation and a method of forming the same are disclosed.

摘要翻译： 形成用于压印光刻的模板的方法。 该方法包括提供紫外（“UV”）波长辐射透明层并通过光刻在UV透明层中形成图案。 图案可以通过各向异性蚀刻UV透明层而形成，并且可以具有小于约100nm的特征尺寸，例如小于约45nm的尺寸。 该方法的另外的实施例包括提供包括其中的第一图案的UV不透明层，形成与UV不透明层的第一图案接触的第一UV透明层，形成与第一UV透明层接触的第二UV透明层 ，并除去UV不透明层以形成模板。 还公开了用于压印光刻的中间模板结构。 在其它实施例中，公开了对UV波长辐射不透明的模板及其形成方法。

公开(公告)号：US20100210111A1

公开(公告)日：2010-08-19

申请号：US12769071

申请日：2010-04-28

申请人： Luan Tran ,  William T. Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi (Jenny) Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer K. Abatchev ,  Gurtej S. Sandhu ,  D. Mark Durcan

发明人： Luan Tran ,  William T. Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi (Jenny) Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer K. Abatchev ,  Gurtej S. Sandhu ,  D. Mark Durcan

IPC分类号： H01L21/308

CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088

摘要： Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern. Pitch multiplication is accomplished by patterning an amorphous carbon layer. Sidewall spacers are then formed on the amorphous carbon sidewalls which are then removed; the sidewall spacers defining the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is transferred to the BARC. The combined pattern is transferred to an underlying amorphous silicon layer. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, is then etched into the underlying substrate.

摘要翻译： 通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。 间距乘法用于形成第一模式的相对较小的特征。 通过图案化无定形碳层来实现间距倍增。 然后在非晶碳侧壁上形成侧壁间隔物，然后将其去除; 侧壁间隔物限定第一掩模图案。 然后沉积底部抗反射涂层（BARC）以形成平坦表面，并且在BARC上形成光致抗蚀剂层。 接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，其转移到BARC。 将组合图案转移到下面的非晶硅层。 然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。 然后将组合的掩模图案蚀刻到下面的基底中。